Senior HSIO Verification Engineer (Equity Eligible)

NVIDIA; Westford (MA); On-site; USD 136,000 - 265,000; Full time

Benefits offered by this job

Equity

Benefits package

Job summary

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of next-generation High Speed I/O controllers for GPUs and SoCs. You will work across IP/sub-system levels using advanced DV methodologies (UVM) and collaborate with cross-functional teams to ensure robust verification.

The role involves building reusable verification components, developing test plans, and contributing to a scalable verification infrastructure.

Qualifications

• Bachelor's or Master's degree (or equivalent) with 5+ years of relevant experience.
• Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM.
• Expertise in verification of IP or interconnect protocols (Ethernet, USB, SATA).
• Experience with random stimulus, functional coverage, assertion-based verification (UVM).
• Excellent debugging and analytical skills; strong collaboration across teams.

Responsibilities

• Verify ASIC design, architecture, and HSIO controller verification at IP/sub-system level using UVM.
• Build reusable bus functional models, monitors, checkers, and scoreboards with coverage-driven verification.
• Develop test plans, tests, and verification infrastructure to ensure design correctness.
• Collaborate with architects, designers, and pre/post-silicon verification teams.

Skills

SystemVerilog

UVM

Verification strategies

Debugging

Communication

Education

Bachelor's or Master's degree

Tools

Perl

Python

Verification tools

Job description

NVIDIA is seeking a Senior Design Verification Engineer to verify the design and implementation of next-generation High Speed I/O controllers for GPUs and SoCs. You will work across IP/sub-system levels using advanced DV methodologies (UVM) and collaborate with cross-functional teams to ensure robust verification.

The role involves building reusable verification components, developing test plans, and contributing to a scalable verification infrastructure.