Custom SOC IP Verification Engineer

NVIDIA; Austin (TX); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify next‑gen SoC and IP solutions in Austin, TX. The role emphasizes fabric and interconnect verification across IP and full‑chip integration with SystemVerilog and UVM expertise.

You will develop test plans, build constrained‑random and directed testbenches, and collaborate with Architecture, SW/HW, and Validation teams to ensure first‑time-right verification and robust strategies.

Qualifications

• BS or MS in Computer/Electrical Engineering or equivalent experience.
• 6+ years of ASIC verification experience focusing on fabric/interconnect or NoC verification at IP and full chip levels.
• Strong SystemVerilog and UVM knowledge.
• Hands-on experience with bus protocols (AMBA AXI, CHI) and understanding of ordering, coherency, and flow control.

Responsibilities

• Verify ASIC fabric and interconnect IP blocks and full-chip integration (DMA, routing, arbitration, ordering, flow control).
• Develop and implement test plans for fabric/interconnect verification in UVM environments at IP and system level.
• Create constrained-random and directed SystemVerilog testbenches for interconnect fabrics and NoC topologies.
• Collaborate with Architecture, SW/HW, Design, Modeling, Emulation, and Post‑Silicon Validation teams.
• Drive silicon/platform verification strategies for fabric and interconnect subsystems.

Skills

SystemVerilog

UVM

Fabric verification

Interconnect verification

Python

Perl

TCL

AMBA AXI

CHI

NoC topologies

Multi-initiator/multi-target intercon

SoC verification

Education

B.S. or M.S. in Computer/Electrical Engineering (or equivalent)

Tools

SystemVerilog/UVM

Job description

NVIDIA is seeking a Senior Custom SOC/IP Verification Engineer to verify the next generation SoC and IP solutions. The role requires expertise in fabric and interconnect verification, spanning both IP and SoC integration, and a deep knowledge of SystemVerilog and UVM.

What You’ll Be Doing

• Responsible for ASIC design verification of fabric and interconnect IP blocks as well as full chip integration, covering DMA, routing, arbitration, ordering, flow control, and protocol compliance.
• Develop and implement test plans for fabric and interconnect verification of SoCs using UVM‑based environments, targeting both IP‑level and system‑level scenarios.
• Design and implement constrained‑random and directed SystemVerilog testbenches targeting interconnect fabrics, network‑on‑chip (NoC) topologies, and multi‑agent SoC integrations.
• Collaborate extensively with Architecture, SW/FW, Design, Modeling, Emulation, and Post‑Silicon Validation teams to ensure comprehensive first‑time‑right verification plans and execution.
• Drive the development of silicon and platform verification strategies and methodologies for fabric and interconnect subsystems.

What We Need to See

• B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or a related field (or equivalent experience).
• 6+ years of experience in ASIC verification, with a strong focus on fabric, interconnect, or network‑on‑chip verification at both IP and full chip levels.
• Strong knowledge of SystemVerilog and UVM methodology.
• Hands‑on experience with industry‑standard interconnect and bus protocols (e.g., AMBA AXI, CHI, or equivalent), with a solid understanding of ordering, coherency, and flow control semantics.
• Familiarity with SoC architectures, NoC topologies, and multi‑initiator/multi‑target interconnect designs.
• Proficiency in scripting languages (Python, Perl, TCL).

Ways to Stand Out from the Crowd

• Knowledge of performance verification and bandwidth/latency analysis for interconnect fabrics.
• Exposure to verification IPs for bus protocols, or emulation platforms (e.g., Palladium, Veloce) for full‑chip fabric validation.
• Experience in GPU or AI accelerator SoC interconnect verification is desirable.
• Experience with formal verification or assertion‑based verification (SVA) applied to fabric and protocol properties.

Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD – 264,500 USD for Level 4, and 196,000 USD – 310,500 USD for Level 5. You will also be eligible for equity and benefits.

Equal Opportunity Employer

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity, we do not discriminate on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status, or any other characteristic protected by law.