Senior Emulation Architect - Pre-Silicon Validation

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 207,000 - 230,000; Full time

Benefits offered by this job

Discretionary bonus

Competitive benefits

Relocation assistance

Job summary

Astera Labs in San Jose, CA seeks a Principal Emulation Engineer to build and operate emulation environments for stress-testing complex ASICs and SoCs prior to silicon. You will lead cross-functional verification with design, firmware and systems teams, and validate PCI Express, CXL, Ethernet, DDR, NVMe and related interfaces across pre-silicon validation, with hands-on debugging and technical leadership.

You will contribute to a robust verification strategy, scale-up emulation workflows, and

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 8–12 years in SoC/silicon verification for server/storage/networking.
• Experience with hardware-software interfaces on complex SoCs.
• Proficient with PCIe Gen3+ and similar protocols (CXL, Ethernet, NVMe, SPI, I2C/I3C).
• Strong SystemVerilog and verification environments.
• Scripting in Python, Perl, C, or similar languages.
• Authorized to work in the United States; able to start immediately.

Responsibilities

• Architect, build, and maintain emulation environments for ASICs and SoCs.
• Integrate RTL, transactors, models, software and test infra for co-simulation.
• Enable stress-testing with scalable, repeatable emulation workflows.
• Debug and lead cross-functional verification to drive issue resolution.
• Provide technical leadership and clear communication with minimal supervision.

Skills

SystemVerilog

SoC verification

Python

C/C++

PCIe/CXL

Emulation prototyping

Technical leadership

Education

Bachelor's degree in Electrical Engineering/CS

Master's degree in EE/CS (preferred)

Tools

Palladium

Zebu

Veloce

HAPS

FPGA prototyping

Job description

Astera Labs in San Jose, CA seeks a Principal Emulation Engineer to build and operate emulation environments for stress-testing complex ASICs and SoCs prior to silicon. You will lead cross-functional verification with design, firmware and systems teams, and validate PCI Express, CXL, Ethernet, DDR, NVMe and related interfaces across pre-silicon validation, with hands-on debugging and technical leadership.

You will contribute to a robust verification strategy, scale-up emulation workflows, and