Pre-Silicon Validation Engineer - Emulation & AI-Assisted Debug

QUALCOMM, Inc.; San Diego (CA); Presencial; USD 101.000 - 152.000; Jornada completa

Descripción de la vacante

QUALCOMM, Inc. in San Diego is seeking a Junior/Senior Emulation Engineer to support design validation for ASIC/FPGA-based systems.

You will develop emulation environments, port RTL to Palladium/Veloc e/Synopsys platforms, and collaborate across RTL, verification, architecture and software teams for co-validation. The role emphasizes SystemVerilog, C/C++, Linux, and Python, with opportunities to apply AI-assisted tools for faster regression, debugging, and data analysis.

Formación

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 0-2+ years of experience in ASIC verification, FPGA prototyping, or hardware emulation.
• Strong expertise in SystemVerilog, C/C++, Linux environment and shell scripting, Python, and ASIC/FPGA emulation platforms.
• Experience with RTL debugging, waveform analysis, and design verification methodologies.
• Knowledge of SoC architectures, bus protocols, and hardware/software interactions.

Responsabilidades

• Develop, deploy, and maintain ASIC/FPGA emulation environments for complex SoC designs.
• Port RTL designs onto Palladium, Protium, Siemens Veloce, or FPGA prototyping systems.
• Collaborate with RTL, verification, architecture, and software teams for co-validation.
• Develop testbenches, transactors, and verification infrastructure using SystemVerilog and C/C++.
• Analyze and debug functional, performance, and system-level issues in emulation environments.
• Create automation scripts and workflows using Python to improve productivity and regression execution.
• Collaborate with design teams to optimize emulation performance and resource utilization.
• Develop methodologies for waveform analysis, signal tracing, and failure root-cause identification.
• Apply AI-assisted tools to accelerate verification, debug, data analysis, and productivity.
• Generate technical documentation and present findings to cross-functional teams.

Conocimientos

SystemVerilog

C/C++

Linux

Python

ASIC Emulation

FPGA Prototyping

Educación

Bachelor's degree

Master's degree

Herramientas

Cadence Palladium

Protium

Siemens Veloce

Synopsys ZeBu

Descripción del empleo

QUALCOMM, Inc. in San Diego is seeking a Junior/Senior Emulation Engineer to support design validation for ASIC/FPGA-based systems.

You will develop emulation environments, port RTL to Palladium/Veloc e/Synopsys platforms, and collaborate across RTL, verification, architecture and software teams for co-validation. The role emphasizes SystemVerilog, C/C++, Linux, and Python, with opportunities to apply AI-assisted tools for faster regression, debugging, and data analysis.