Principal Emulation and Validation Engineer

WinMax Systems Corporation; San Jose (CA); On-site; USD 130,000 - 160,000; Full time

Job summary

A leading technology company in San Jose is seeking a Principal Emulation and Validation Engineer to work on complex system-on-chip designs and enhance verification methods. The ideal candidate must have significant experience in ASIC verification, strong programming skills in C/C++, Tcl, and Python, and a passion for problem-solving. Responsibilities include synthesizing designs for hardware emulators, developing system-level tests, and maintaining emulation environments. This full-time position offers opportunities for innovation and collaboration within high-profile projects.

Qualifications

• Minimum 12 years experience with BS, 9 years with MS, or 6 years with a PhD.
• Hands-on experience with ASIC/SoC verification methodologies.
• Strong analytical and problem-solving skills.
• Excellent structured programming skills required.

Responsibilities

• Synthesize system on chip designs for hardware emulators.
• Develop system level tests using various programming languages.
• Create design blocks and verification components for emulation.
• Debug and resolve silicon failures effectively.
• Maintain emulation environment for global users.

Skills

Verilog

System Verilog

Tcl

iTcl

Perl

Python

C/C++

Unix Scripting

Debugging

Project Management

Education

BS in Electrical Engineering or Computer Science

MS in Electrical Engineering or Computer Science

PhD

Job description

Principal Emulation and Validation Engineer

Job Type: Full-time

Responsibilities

• Synthesize complex system on chip designs and map into various hardware emulator platforms like Cadence Palladium or Mentor Veloce.
• Develop system level tests using tcl, itcl, python, C/C++ languages to verify networking switch chips and systems.
• Create reusable design blocks, libraries and verification components for emulation.
• Improve and define new verification / emulation methodologies.
• Debug and resolve Pre / Post Silicon failures.
• Create and maintain emulation environment for worldwide user community.
• Write Complex Device Driver using C/C++ to implement feature on a flexible architecture and support and promote with wide range customer adoption.

Job Requirements

• Total engineering minimum experience required is typically a BS degree and 12+ years of experience, an MS degree and 9+ years of experience or a PhD and 6 years of experience or equivalent.
• BS (EE/Electrical Engineering or CS/Computer Science) required, MS (EE or CS) preferred or equivalent.
• Hands-on experience with Leadership qualities on driving ASIC / SoC verification flows and methodologies.
• Must have hands-on experience with network protocol validation, RFC, IEEE, etc.
• Good Knowledge in languages relevant to the ASIC verification process including Verilog, System Verilog, Tcl, iTcl, Perl, Python, Ruby, C/C++ and Unix Scripting.
• Strong expertise in writing system level tests and driver using C/C++, Tcl, iTcl, Perl and Python.
• Excellent structured programming skills, data structures, algorithms, SCM for large complex SW projects. Automation experience is a plus.
• Strong Pre/Post Silicon debugging, analytical and independent problem solving ability.
• Good knowledge in using industry standard debugging tools for both HW & SW.
• Must be a team player with good verbal and written communication skills.
• Must be self-driven engineer with good project management and organizational skills to deliver high quality output in a timely manner.
• All your information will be kept confidential according to EEO guidelines.