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Job summary
A leading technology company in San Jose is seeking a Principal Emulation and Validation Engineer to work on complex system-on-chip designs and enhance verification methods. The ideal candidate must have significant experience in ASIC verification, strong programming skills in C/C++, Tcl, and Python, and a passion for problem-solving. Responsibilities include synthesizing designs for hardware emulators, developing system-level tests, and maintaining emulation environments. This full-time position offers opportunities for innovation and collaboration within high-profile projects.
Qualifications
Minimum 12 years experience with BS, 9 years with MS, or 6 years with a PhD.
Hands-on experience with ASIC/SoC verification methodologies.
Strong analytical and problem-solving skills.
Excellent structured programming skills required.
Responsibilities
Synthesize system on chip designs for hardware emulators.
Develop system level tests using various programming languages.
Create design blocks and verification components for emulation.
Debug and resolve silicon failures effectively.
Maintain emulation environment for global users.
Skills
Verilog
System Verilog
Tcl
iTcl
Perl
Python
C/C++
Unix Scripting
Debugging
Project Management
Education
BS in Electrical Engineering or Computer Science
MS in Electrical Engineering or Computer Science
PhD
Job description
A leading technology company in San Jose is seeking a Principal Emulation and Validation Engineer to work on complex system-on-chip designs and enhance verification methods. The ideal candidate must have significant experience in ASIC verification, strong programming skills in C/C++, Tcl, and Python, and a passion for problem-solving. Responsibilities include synthesizing designs for hardware emulators, developing system-level tests, and maintaining emulation environments. This full-time position offers opportunities for innovation and collaboration within high-profile projects.