Senior SoC Verification Architect (SystemVerilog/UVM)

Hardware FYI; San Jose (CA); Sur place; USD 185 000 - 230 000; Plein temps

Avantages offerts par ce poste

Discretionary bonus

Benefits package

Résumé du poste

Astera Labs is seeking a Principal Design Verification Engineer in San Jose, CA to advance verification methodologies for cutting-edge SoCs used in server and networking applications.

The ideal candidate has 8+ years in SoC verification, strong SystemVerilog/UVM expertise, and experience with emulation platforms, test planning, and coverage closure. A Bachelor’s in Electrical Engineering is required; a Master’s is preferred. Competitive salary and benefits offered.

Qualifications

• Bachelor’s degree in Electrical Engineering (Master’s preferred).
• 8+ years of SoC verification experience, particularly for server and networking applications.
• Expertise in SystemVerilog/UVM and full verification lifecycle.
• Proficiency with industry-standard simulators, version control, and regression systems.
• Strong debugging and coverage analysis skills.
• Experience developing and executing test sequences, generating stimuli, and identifying verification holes.
• Familiarity with verification of switching architectures, including packet processing and forwarding engines.
• Excellent communication skills and ability to work independently with minimal supervision.

Responsabilités

• Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis.
• Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms.
• Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools.
• Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification.
• Work with RTL designers to troubleshoot and resolve design issues.
• Drive verification strategy and methodology for SoCs in server and networking applications.

Connaissances

SystemVerilog/UVM

Debugging

Coverage analysis

Test sequences

Scripting (Python/C++)

Formation

Bachelor’s degree in Electrical Engineering

Master’s preferred

Outils

Simulators

Version control

Regression systems

Emulation platforms

Description du poste

Astera Labs is seeking a Principal Design Verification Engineer in San Jose, CA to advance verification methodologies for cutting-edge SoCs used in server and networking applications.

The ideal candidate has 8+ years in SoC verification, strong SystemVerilog/UVM expertise, and experience with emulation platforms, test planning, and coverage closure. A Bachelor’s in Electrical Engineering is required; a Master’s is preferred. Competitive salary and benefits offered.