Senior ASIC Emulation Engineer — Hybrid/Onsite Impact

Palo Alto Networks, Inc.; Santa Clara (CA); Hybride; USD 180 000 - 280 000; Plein temps

Résumé du poste

Palo Alto Networks, Inc. is seeking a Senior/Lead ASIC Emulation Engineer to drive emulation architecture, verify complex SoCs, and bridge hardware design with software bring-up.

You will collaborate with Design, Verification, and Software teams, build scalable emulation environments, and push pre-silicon validation. The role emphasizes leadership and hands-on expertise in major emulation platforms.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or equivalent practical experience.
• 8+ years hands-on hardware emulation, FPGA prototyping, and ASIC verification experience.
• Experience with Palladium, ZeBu, or Veloce hardware emulation platforms.
• Strong SystemVerilog/Verilog, C/C++, and UVM/DPI skills.
• Familiar with platform debugging tools and co-emulation interfaces.

Responsabilités

• Architect and maintain enterprise-scale emulation platforms (Palladium/ZeBu/Veloce).
• Collaborate with ASIC Architecture, Design, Verification, and Software teams on pre-silicon plans.
• Synthesize and fit multi‑million/billion‑gate SoCs on emulation hardware; optimize power and timing.
• Develop transactors, adapters, and virtual/physical interfaces (PCIe, Ethernet, DDR, CXL).
• Enable pre-silicon software bring-up and OS/driver validation on emulation platforms.
• Debug deep hardware/firmware/protocol issues with waveform captures and probes.
• Automate build/regression flows using Python, Tcl, and CI/CD tools.
• Work with post-silicon validation to reproduce silicon anomalies on emulation.

Connaissances

Hardware emulation

SystemVerilog

Verilog

C/C++

UVM/DPI interfaces

Cross-functional collaboration

Automation/scripting

Formation

BS/MS in Electrical Engineering, Computer Engineering, or Computer Science

Outils

Cadence Palladium

Synopsys ZeBu

Siemens Veloce

SimVision

Indago

Verdi

PCIe

Ethernet

DDR

CXL

Description du poste

Palo Alto Networks, Inc. is seeking a Senior/Lead ASIC Emulation Engineer to drive emulation architecture, verify complex SoCs, and bridge hardware design with software bring-up.

You will collaborate with Design, Verification, and Software teams, build scalable emulation environments, and push pre-silicon validation. The role emphasizes leadership and hands-on expertise in major emulation platforms.