Senior Emulation Architect — AI ASIC (Pre-Silicon)

Positron Corporation; United States; Remote; USD 180,000 - 300,000; Full time

Benefits offered by this job

Health insurance

Job summary

Positron AI seeks a Lead Emulation Engineer to provide technical leadership for pre-silicon validation of its AI inference ASIC. You will own end-to-end emulation strategy on Cadence Palladium, architect multi-rack designs, and drive software left-shift across RTL, DV, and Software teams to accelerate tape-out.

You will lead complex model builds, optimize performance, and ensure silicon-readiness while collaborating with Cadence R&D and internal teams.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years in ASIC Emulation or Verification with Palladium experience.
• Mastery of SystemVerilog, Verilog, and C/C++ for transactor development.
• Deep understanding of PCIe, DDR, and AMBA AXI/NoC.

Responsibilities

• Lead partitioning and compilation across multi-rack Palladium for performance and debug visibility.
• Create and maintain hybrid emulation and co-simulation environments enabling OS boot and AI workloads on pre-silicon hardware.
• Design and execute emulation test plans for high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and AI memory hierarchies.
• Use Palladium Dynamic Power Analysis and throughput monitors to identify true peaks and bottlenecks.
• Act as main technical contact with Cadence R&D and leverage Palladium Z3 capabilities.

Skills

Palladium expertise

SoC emulation

Automation scripting

Debug tools

Education

BS/MS in Electrical/Computer Engineering or Computer Science

Tools

Python

Tcl

Bash

Verdi

SimVision

VIF

Job description

Positron AI seeks a Lead Emulation Engineer to provide technical leadership for pre-silicon validation of its AI inference ASIC. You will own end-to-end emulation strategy on Cadence Palladium, architect multi-rack designs, and drive software left-shift across RTL, DV, and Software teams to accelerate tape-out.

You will lead complex model builds, optimize performance, and ensure silicon-readiness while collaborating with Cadence R&D and internal teams.