Palladium Emulation Architect - Pre-Silicon AI ASIC

Positron AI; Austin (TX); On-site; USD 180,000 - 300,000; Full time

Benefits offered by this job

Med, Dental & Vision insurance

Life & Disability coverage

Unlimited PTO

Job summary

Positron AI is hiring an Emulation Test Engineer to lead pre-silicon validation of AI inference ASICs using Cadence Palladium. You will architect multi-rack environments, drive left-shift of software, and work with RTL, DV, and Software teams to validate interfaces and memory hierarchies.

The role requires 8+ years in ASIC Emulation, SystemVerilog/Verilog/C/C++, and deep Palladium experience. Eligibility for US work authorization applies. Remote-first culture with competitive compensation]

Qualifications

• Deep Palladium expertise with clocking, ICE, and VIF flows.
• Experience emulating multi-billion gate designs and large Palladium installs.
• Proficient in Python, Tcl, and Bash for automation.
• Debugging firmware and kernel issues with Verdi/SimVision.

Responsibilities

• Lead partitioning and compilation across multi-rack Palladium environments.
• Create and maintain hybrid emulation and co-simulation environments.
• Design and execute emulation test plans for high-speed interfaces.
• Perform power and performance analysis using Palladium tools.
• Manage Cadence R&D interactions and tool problem resolution.

Skills

Palladium expertise

SoC emulation

Automation master

Hardware-software debugging

BS/MS in EE/CS

8+ years ASIC emulation

SystemVerilog/Verilog/C/C++

PCIe/DDR/AXI/NoC protocols

Education

BS/MS in Electrical Engineering/Computer Engineering/CS

Tools

Cadence Palladium (Z1/Z2/Z3)

SCE-MI/DPI

Verdi

SimVision

Job description

Positron AI is hiring an Emulation Test Engineer to lead pre-silicon validation of AI inference ASICs using Cadence Palladium. You will architect multi-rack environments, drive left-shift of software, and work with RTL, DV, and Software teams to validate interfaces and memory hierarchies.

The role requires 8+ years in ASIC Emulation, SystemVerilog/Verilog/C/C++, and deep Palladium experience. Eligibility for US work authorization applies. Remote-first culture with competitive compensation]