Emulation Engineer, Lead

Positron Corporation; United States; Remote; USD 180,000 - 300,000; Full time

Benefits offered by this job

Health insurance

Job summary

Positron AI seeks a Lead Emulation Engineer to provide technical leadership for pre-silicon validation of its AI inference ASIC. You will own end-to-end emulation strategy on Cadence Palladium, architect multi-rack designs, and drive software left-shift across RTL, DV, and Software teams to accelerate tape-out.

You will lead complex model builds, optimize performance, and ensure silicon-readiness while collaborating with Cadence R&D and internal teams.

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• 8+ years in ASIC Emulation or Verification with Palladium experience.
• Mastery of SystemVerilog, Verilog, and C/C++ for transactor development.
• Deep understanding of PCIe, DDR, and AMBA AXI/NoC.

Responsibilities

• Lead partitioning and compilation across multi-rack Palladium for performance and debug visibility.
• Create and maintain hybrid emulation and co-simulation environments enabling OS boot and AI workloads on pre-silicon hardware.
• Design and execute emulation test plans for high-speed interfaces (PCIe Gen 6/7, 112G+VSR, Ethernet) and AI memory hierarchies.
• Use Palladium Dynamic Power Analysis and throughput monitors to identify true peaks and bottlenecks.
• Act as main technical contact with Cadence R&D and leverage Palladium Z3 capabilities.

Skills

Palladium expertise

SoC emulation

Automation scripting

Debug tools

Education

BS/MS in Electrical/Computer Engineering or Computer Science

Tools

Python

Tcl

Bash

Verdi

SimVision

VIF

Job description

About the role

As a Lead Emulation Engineer , you will provide technical leadership for the pre-silicon validation of Positron.ai’s next-generation AI inference ASIC. You will own the end-to-end emulation strategy on the Cadence Palladium platform—architecting complex model builds, managing multi-rack partitioning, and driving the ‘left-shift’ of our software development. You will collaborate across RTL, DV, and Software teams to build high-performance virtual environments that prove out architectural functionality and accelerate firmware/OS bring-up months before tape-out. This role is critical to our silicon success: you will set the emulation methodology, resolve hardware-software bottlenecks at scale, and ensure our design is silicon-ready.

What you’ll do

• Massive-Scale Model Architecture: Lead the partitioning and compilation of our design across a multi-rack Palladium environment, optimizing for performance and debug visibility.
• Software Enablement (Left-Shift): Create and maintain the hybrid emulation and co-simulation environments (using SCE-MI or DPI ) that allow our software teams to boot OS images and run AI workloads on pre-silicon hardware.
• Full-Stack Validation: Design and execute comprehensive emulation test plans to verify high-speed interfaces ( PCIe Gen 6/7, 112G+VSR, Ethernet ) and complex AI memory hierarchies.
• Performance & Power Analysis: Utilize Palladium’s Dynamic Power Analysis (DPA) and throughput monitors to identify “true peaks” and performance bottlenecks that simulation cannot capture.
• Vendor Management: Act as the primary technical point of contact with Cadence R&D to troubleshoot tool issues and leverage the latest Palladium Z3 capabilities.

You’ll Be Successful Here if You Have

• Deep Palladium Expertise: Extensive hands-on experience with Cadence Palladium (Z1/Z2/Z3), including advanced clocking, ICE (In-Circuit Emulation), and Virtual Interface (VIF) flows
• Complex SoC Background: A track record of emulating multi-billion gate designs where partitioning, runtime predictability, and compile efficiency were critical success factors
• Automation Mastery: Expert-level Python , Tcl , and Bash skills to build and maintain the infrastructure for automated model releases and nightly regressions
• Hardware-Software Debug Skills: Proficiency in debugging low-level firmware and kernel-level issues using Verdi , SimVision , and hardware-software co-debug tools

Minimum Requirements

• Education: BS/MS in Electrical Engineering, Computer Engineering, or Computer Science.
• Experience: 8+ years in ASIC Emulation or Verification, with significant experience on large-scale Palladium installations
• Technical Skills: Mastery of SystemVerilog , Verilog , and C/C++ for transactor development and reference modeling.
• Protocol Knowledge: Deep understanding of data center protocols including PCIe , DDR and AMBA AXI/NoC

Leveling & Scope

While this role is currently posted at a specific level, we are a growth-oriented organization and are open to hiring at a more senior level for the right candidate. Please note that this job description serves as a focused but generalized overview of the role; specific responsibilities and impact expectations will be tailored to the experience and seniority of the final hire.

Compensation & Benefits

The base salary range for this role is $180,000 – $300,000.

Please note that the figures provided represent the base salary range only and do not include other elements of our total compensation package, equity, or comprehensive benefits.

At Positron AI, we value the unique expertise each candidate brings. While the range above reflects our typical expectation for the position, we reserve the flexibility to exceed this range for candidates whose specialized skills, significant experience, or unique qualifications fall outside the standard scope of the role. Final offers are determined based on a variety of factors, including internal equity, and individual impact.

Equal Opportunity Employer. If you’re excited about the role but don’t meet every bullet, we’d still love to hear from you.