Senior DRAM IO/Clock Design Architect — MTS

Micron Technology, Inc; Boise (ID); On-site; USD 190,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. seeks a Principal/Member of Technical Staff (MTS) IO/Clock Design Eng to join the DRAM IP Design team for high-speed IP circuits used in Micron's DRAM products.

Relocation to Boise, Idaho is required; you will develop, verify, and optimize IO and clocking circuits, analyze timing, jitter and duty cycle impacts, and drive AI-assisted design methods. Responsibilities include modeling, simulation, and collaboration with process and data science teams to push performance in

Qualifications

• Design high-speed IO interface and clocking circuits with proven silicon experience.
• Lead layout supervision to minimize parasitics in high-speed circuits.
• Excellent communication to share technical concepts with peers.

Responsibilities

• Innovate, design, optimize and verify high-speed IO and clocking circuits in DRAM products.
• Assess timing and jitter sensitivity at circuit and full-chip levels.
• Develop modeling and simulation methods for key circuit metrics and their impact on specs.
• Collaborate with Product Engineering and SI teams to compare silicon with simulations.
• Work with process integration and transistor modeling teams on new process nodes.
• Collaborate with data science teams and AI vendors to improve AI-assisted design flow.

Skills

High-speed IO

Clocking circuits

Timing analysis

Mentoring engineers

Python/Perl scripting

AI-assisted design

Education

MSEE with 10+ years

BSEE with 12+ years

Tools

PERL

Python

Job description

Micron Technology, Inc. seeks a Principal/Member of Technical Staff (MTS) IO/Clock Design Eng to join the DRAM IP Design team for high-speed IP circuits used in Micron's DRAM products.

Relocation to Boise, Idaho is required; you will develop, verify, and optimize IO and clocking circuits, analyze timing, jitter and duty cycle impacts, and drive AI-assisted design methods. Responsibilities include modeling, simulation, and collaboration with process and data science teams to push performance in