DRAM IP Architect — High‑Speed IO & Clocking Lead

Micron Technology, Inc; Boise (ID); On-site; USD 180,000 - 240,000; Full time

Job summary

Micron Technology, Inc is seeking a Principal SMTS for DRAM IP design to architect, design and verify high-speed IO and clocking circuits for next‑generation DRAM products, focusing on timing, jitter, and signal integrity. Relocation to Boise, ID is required; the role involves collaboration with Product Engineering, SI and process teams to push performance while mentoring junior engineers.

Candidates should have MSEE with 10+ years or BSEE with 12+ years, plus strong communication and leadership

Qualifications

• PhD not required; requires a minimum MSEE with 10+ years in high-speed IO and clocking design.
• Ability to supervise layout and minimize parasitics in high-speed circuits.
• Excellent written and verbal communication to collaborate across teams.

Responsibilities

• Define, innovate, design, optimize and verify high-speed IO and clocking circuits used in new DRAM products.
• Apply robust high-speed circuit design techniques and assess timing and jitter sensitivity at circuit and full-chip level.
• Develop modeling, analysis and simulation methodologies to capture core performance metrics and impact on specs.
• Collaborate with Product Engineering and SI to compare silicon vs. simulations and support correlation.
• Work with process integration and transistor modeling teams on future nodes.

Skills

High-speed IO

Clocking circuits

Timing analysis

Jitter analysis

Silicon verification

Mentoring

Python scripting

Perl scripting

Channel modeling

AI/ML usage

Education

MSEE

BSEE

Tools

SPICE Simulation

Modeling Tools

Job description

Micron Technology, Inc is seeking a Principal SMTS for DRAM IP design to architect, design and verify high-speed IO and clocking circuits for next‑generation DRAM products, focusing on timing, jitter, and signal integrity. Relocation to Boise, ID is required; the role involves collaboration with Product Engineering, SI and process teams to push performance while mentoring junior engineers.

Candidates should have MSEE with 10+ years or BSEE with 12+ years, plus strong communication and leadership