Senior Digital Verification Engineer - FPGA/ASIC & Security

Draper; Cambridge (MA); On-site; USD 75,000 - 156,000; Full time

Benefits offered by this job

Workplace flexibility

Health workshops

Social events

Museum discounts

Job summary

Draper in Cambridge, MA seeks an experienced UVM Digital Verification Engineer to tackle verification challenges in FPGA and ASIC designs. You will develop verification strategies, build UVM environments, and collaborate with RTL teams to deliver robust hardware platforms.

The role requires 3–5 years in IC/ASIC engineering or 0–2 years with a master’s, plus strong SystemVerilog/SVA/UVM expertise. On-site in Cambridge with competitive salary and benefits.

Qualifications

• Requires 3–5 years of IC/ASIC hardware engineering with a bachelor’s.
• Master’s degree preferred.

Responsibilities

• Design and simulate circuits at transistor level to meet specs.
• Contribute to system-level design and optimization for performance, power, and cost.
• Develop verification approaches, plans, and UVM testbenches.
• Create and instantiate UVM agents and VIPs for standard buses.
• Collaborate with RTL designers to resolve simulation issues and ensure coverage.

Skills

IC design

Digital verification

UVM

SystemVerilog

SVA

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

QuestaSim

Xcelium

VCS

Job description

Draper in Cambridge, MA seeks an experienced UVM Digital Verification Engineer to tackle verification challenges in FPGA and ASIC designs. You will develop verification strategies, build UVM environments, and collaborate with RTL teams to deliver robust hardware platforms.

The role requires 3–5 years in IC/ASIC engineering or 0–2 years with a master’s, plus strong SystemVerilog/SVA/UVM expertise. On-site in Cambridge with competitive salary and benefits.