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Draper Laboratory in Cambridge, MA seeks a Senior Digital ASIC Designer to create high-performance digital ASICs in advanced technologies. Responsibilities include RTL-to-synthesis implementation, system-level design, and mentoring junior engineers.
Ideal candidates bring 7–10 years of ASIC hardware experience, SystemVerilog/Verilog/VHDL fluency, and a track record of successful tape-outs. On-site work in Cambridge with eligibility for US security clearance is required.
Draper Laboratory in Cambridge, MA seeks a Senior Digital ASIC Designer to create high-performance digital ASICs in advanced technologies. Responsibilities include RTL-to-synthesis implementation, system-level design, and mentoring junior engineers.
Ideal candidates bring 7–10 years of ASIC hardware experience, SystemVerilog/Verilog/VHDL fluency, and a track record of successful tape-outs. On-site work in Cambridge with eligibility for US security clearance is required.