Senior ASIC Verification Engineer - SystemVerilog/UVM

Teradyne; North Reading (MA); On-site; USD 123,000 - 197,000; Full time

Job summary

Teradyne in North Reading, MA seeks an ASIC Verification Engineer to join the Reference Model team. You will verify complex ASIC/SoC designs using SystemC, SystemVerilog/UVM, and constrained-random methods, collaborating with design, firmware, and software groups.

The role emphasizes verification planning, testbench architecture, and delivering high-quality results with rigorous methodologies. Bachelor’s degree required; Master’s preferred, with 4+ years in semiconductor verification.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
• 4+ years of ASIC/SoC verification experience in semiconductor product development.
• Experience with SystemC and C++.
• Object Oriented Programming experience.
• Experience developing verification environments using SystemVerilog and UVM.
• Deep understanding of functional verification methodologies, constrained-random verification, and coverage closure.

Responsibilities

• Verification planning, testbench architecture, and execution for complex ASIC and SoC designs.
• Develop and maintain SystemC and SystemVerilog/UVM reference models.
• Develop and maintain SystemVerilog/UVM-based verification environments, test cases, and reusable verification components.
• Collaborate closely with design, architecture, firmware, software, and validation teams to ensure comprehensive feature coverage.
• Build and execute verification strategies utilizing simulation, coverage-driven verification, assertions, and formal methodologies.
• Support debug and root-cause analysis of functional issues identified during verification and silicon bring-up activities.
• Partner with cross-functional teams to define verification requirements, milestones, and quality metrics.
• Ensure verification deliverables are completed with high quality, on schedule, and aligned with project objectives.

Skills

SystemC

C++

SystemVerilog/UVM

Python/Perl scripting

Functional verification

Constrained-random verification

Formal verification

Debugging complex designs

Silicon bring-up support

Education

Bachelor's degree in Electrical/Computer Engineering/CS

Master's degree preferred

Tools

EDA simulation tools

Job description

Teradyne in North Reading, MA seeks an ASIC Verification Engineer to join the Reference Model team. You will verify complex ASIC/SoC designs using SystemC, SystemVerilog/UVM, and constrained-random methods, collaborating with design, firmware, and software groups.

The role emphasizes verification planning, testbench architecture, and delivering high-quality results with rigorous methodologies. Bachelor’s degree required; Master’s preferred, with 4+ years in semiconductor verification.