Lead Digital ASIC Design Engineer (Onsite Cambridge)

Draper Inc.; Cambridge (MA); On-site; USD 82,300 - 220,000; Full time

Job summary

Draper Laboratory in Cambridge, MA, seeks a Senior Digital ASIC Designer to implement high-performance digital ICs from RTL through synthesis.

Responsibilities include system-level design, optimization for performance and power, and leadership of multidisciplinary teams. Requires 7–10 years (or 5–10 with a Master’s) in ASIC hardware, with Cadence/Synopsys flows and SystemVerilog, Verilog or VHDL proficiency. On-site in Cambridge; US security clearance required.

Qualifications

• Requires 7-10 years of experience with a bachelor's degree or 5-10 years with a master's in ASIC Hardware Engineering or related.
• Experience with low power circuit design and CMOS advanced nodes Below 32nm.
• Experience with radiation-hardened electronics and secure-system architectures is a plus.

Responsibilities

• Design and simulate circuits at transistor-level to implement architecture and requirements.
• Contribute to system-level design and optimize hardware for performance, power, and cost.
• Independently drive complex chip architectures and lead multi-disciplinary teams.

Skills

IC design

SystemVerilog

Verilog

VHDL

RTL design

low power design

digital architectures

team leadership

design-for-test

written communication

Education

Bachelor's degree in Engineering

Master's degree preferred

Tools

Cadence

Synopsys

Job description

Draper Laboratory in Cambridge, MA, seeks a Senior Digital ASIC Designer to implement high-performance digital ICs from RTL through synthesis.

Responsibilities include system-level design, optimization for performance and power, and leadership of multidisciplinary teams. Requires 7–10 years (or 5–10 with a Master’s) in ASIC hardware, with Cadence/Synopsys flows and SystemVerilog, Verilog or VHDL proficiency. On-site in Cambridge; US security clearance required.