Senior Verification Engineer — ASIC/FPGA (Remote)

Fidus Systems; North Carolina; On-site; USD 120,000 - 150,000; Full time

Benefits offered by this job

Medical, dental, vision

401(k) with matching

Profit-sharing bonus

Job summary

Fidus Systems is seeking a Verification Designer to own block- and system-level verification of ASIC and FPGA designs. You will develop UVM, formal, and assertion-based environments, applying CRV techniques to meet coverage goals and ensure robust designs.

The role involves leading verification activities, debugging complex issues, and collaborating with clients and cross-functional teams across the hardware and software domains. Remote-friendly with occasional travel.

Qualifications

• 8+ years of ASIC/FPGA verification experience with verification-lead ownership.
• Strong SystemVerilog and UVM methodology fluency.
• Experience with functional coverage, assertions, and formal verification techniques.

Responsibilities

• Own block- and system-level verification of ASIC and FPGA designs from test plan through coverage closure.
• Design and implement UVM, formal, and assertion-based verification environments; apply CRV techniques.
• Develop behavioral models and write test cases to achieve functional coverage goals.
• Define and track coverage metrics to closure.
• Debug and troubleshoot failures in simulation and regression runs with designers and system architects.
• Automate verification tasks and monitor regressions using scripting (Python, Perl, or Tcl).
• Plan, execute, and report status on multiple verification activities as a verification lead.
• Work directly with external clients on verification strategy and support.

Skills

SystemVerilog

UVM

Constrained-random

CRV

Coverage metrics

Python/Perl/Tcl

Debugging

Client-facing

Artificial intelligence

AI-assisted engineering

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical/Computer Engineering

Tools

cocoTB

pyUVM

DPI-C

Job description

Fidus Systems is seeking a Verification Designer to own block- and system-level verification of ASIC and FPGA designs. You will develop UVM, formal, and assertion-based environments, applying CRV techniques to meet coverage goals and ensure robust designs.

The role involves leading verification activities, debugging complex issues, and collaborating with clients and cross-functional teams across the hardware and software domains. Remote-friendly with occasional travel.