Design Verification Engineer

MaximaTek; Fremont (CA); On-site; USD 90,000 - 130,000; Full time

Benefits offered by this job

Targeted Placement into hiring network

Technical Resume Rebuild

Interview Coaching

Job summary

MaximaTek is seeking a meticulous Design Verification Engineer to oversee ASIC/SoC verification workflows and testbench architecture in Fremont, CA. You will bridge RTL design teams, system architects, and EDA vendors to ensure efficient, scalable verification with strong functional coverage.

The role requires a Bachelor's in an engineering field and 0–5 years of digital design verification experience. Proficiency in SystemVerilog/Verilog/VHDL and scripting languages is expected, with exposure

Qualifications

• Bachelor's degree in a relevant engineering field is required.
• 0–5 years in digital design verification, ASIC/SoC development, or hardware research environments.
• Strong understanding of HDL, scripting, and verification methodologies. Please demonstrate proficiency in SystemVerilog, Verilog, VHDL, Python, Perl or Tcl.

Responsibilities

• Coordinate verification lifecycle activities including test plan development and testbench architecture.
• Manage constrained random stimulus, regression scheduling, and coverage analysis.
• Maintain verification documentation and version control for audits and compliance (e.g., ISO 26262 references).
• Collaborate with RTL design, system architects, and EDA vendors to optimize verification workflows.

Skills

Digital Logic Design

Computer Architecture

Verification Methodologies

SystemVerilog

Verilog

VHDL

Python

Perl

Tcl

Education

Bachelor's degree in Electrical Engineering or related field

Tools

Synopsys VCS

Cadence Xcelium

Siemens Questa

Job description

About the Role

Design Verification Engineer

We are seeking a detail-oriented Design Verification Engineer to manage and oversee the daily operations of our ASIC/SoC verification workflows and testbench architecture. In this role, you will act as the vital link between our RTL design teams, system architects, and EDA tool vendors, ensuring that all hardware designs are verified with maximum efficiency, scalability, and adherence to strict functional coverage standards and industry security specifications.

Core Responsibilities

Verification Lifecycle Management: Coordinate daily verification activities, including test plan development, testbench architecture creation, constrained random stimulus generation, and regression scheduling. Regulatory & Functional Compliance: Maintain comprehensive verification documentation and version control; ensure all design activities align with industry security standards, safety frameworks (e.g., ISO 26262), and company SOPs. Data & Signal Integrity: Perform accurate assertion-based verification (SVA) and functional coverage analysis; ensure rigorous verification metrics are applied to simulation logs and hardware specifications. Risk Mitigation: Monitor coverage gaps, bug trends, and simulation performance bottlenecks; report significant design bugs or verification non-compliance promptly to management and stakeholders.

Quality Assurance: Author and maintain test plan specifications; assist in internal and external audits to ensure quality standards and tape-out readiness criteria for complex digital systems are met. Technical Liaison: Serve as the primary point of contact for EDA tool providers and third-party IP vendors during performance reviews and technical audits.

Qualifications

Education: Bachelor’s degree in Electrical Engineering, Electronics Engineering, Computer Engineering, or a related field (Required). Experience: 0–5 years of experience in digital design verification, ASIC/SoC development, or hardware research environments. Technical Skills (Required): Strong understanding of Digital Logic Design, Computer Architecture, and Verification Methodologies (UVM/OVM). Proficiency in hardware description and verification languages (SystemVerilog, Verilog, VHDL) and scripting languages (Python, Perl, Tcl). Familiarity with EDA simulation tools (e.g., Synopsys VCS, Cadence Xcelium, Siemens Questa) and regression management pipelines. Excellent technical writing and organizational skills. Preferred Skills: Experience with Formal Verification tools or Emulation platforms (e.g., Palladium, Zebu). Knowledge of high-speed protocols (PCIe, Ethernet, USB) or bus architectures (AMBA AXI/AHB). Knowledge of low-power verification (UPF/CPF) and mixed-signal simulation.

What We Offer

Targeted Placement: Direct marketing to our network of hiring managers in the Tech, Semiconductor, Manufacturing, and MedTech industries. Technical Resume Rebuild: Optimization of your profile to highlight verification expertise alongside silicon debug efficiency. Interview Coaching: Guidance on technical coding interviews, SystemVerilog/UVM concepts, and hardware verification system design case studies.