Senior Digital IC Design Engineer - RTL to GDSII

IntelliPro; Santa Clara (CA); On-site; USD 150,000 - 300,000; Full time

Job summary

IntelliPro is seeking a Principle Digital IC Design Engineer in Santa Clara, CA or Raleigh, NC to own and optimize the digital RTL-to-GDSII flow for mixed-signal PMICs and high-speed data paths.

You will drive backend synthesis, DFT/MBIST insertion, clock tree design, and timing closure, collaborating with System Architects and layout teams to achieve high-frequency performance and low area/power.

Qualifications

• 10+ years of hybrid digital IC design and physical implementation experience in mixed-signal environments (PMICs, multi-phase controllers, or high-speed data converters).
• Strong RTL coding skills in Verilog or SystemVerilog; ability to read, write, and restructure RTL for optimal physical synthesis.
• Experience inserting DFT/MBIST, complex clock tree structures, and closing timing in constrained physical areas.

Responsibilities

• Digital-on-Top Flow Development: establish and execute the complete digital-on-top P&R methodology; integrate complex digital cores with precision analog blocks.
• Full Backend Execution: drive the digital design through the entire physical pipeline—logic synthesis, DFT/MBIST insertion, MBIST, and routing.
• Physical Optimization & CTS: architect and optimize floorplan, power grid, and CTS; modify RTL to resolve bottlenecks and reduce congestion.
• RTL Design & Architecture: write Verilog/SystemVerilog, design state machines, contribute to top-level architecture with System Architect.
• Timing Closure & Sign-off: own STA, parasitic extraction, and DRC/LVS for digital domains to meet area, power, and high-frequency targets.

Skills

Digital IC design

RTL Verilog/SystemVerilog

Clock tree design

Synthesis/STA

Physical implementation

Tools

Cadence Innovus

Cadence Genus

PrimeTime

Calibre

Job description

IntelliPro is seeking a Principle Digital IC Design Engineer in Santa Clara, CA or Raleigh, NC to own and optimize the digital RTL-to-GDSII flow for mixed-signal PMICs and high-speed data paths.

You will drive backend synthesis, DFT/MBIST insertion, clock tree design, and timing closure, collaborating with System Architects and layout teams to achieve high-frequency performance and low area/power.