Principle Digital IC Design Engineer

IntelliPro; Santa Clara (CA); Presencial; USD 150.000 - 300.000; Jornada completa

Descripción de la vacante

IntelliPro is seeking a Principle Digital IC Design Engineer in Santa Clara, CA or Raleigh, NC to own and optimize the digital RTL-to-GDSII flow for mixed-signal PMICs and high-speed data paths.

You will drive backend synthesis, DFT/MBIST insertion, clock tree design, and timing closure, collaborating with System Architects and layout teams to achieve high-frequency performance and low area/power.

Formación

• 10+ years of hybrid digital IC design and physical implementation experience in mixed-signal environments (PMICs, multi-phase controllers, or high-speed data converters).
• Strong RTL coding skills in Verilog or SystemVerilog; ability to read, write, and restructure RTL for optimal physical synthesis.
• Experience inserting DFT/MBIST, complex clock tree structures, and closing timing in constrained physical areas.

Responsabilidades

• Digital-on-Top Flow Development: establish and execute the complete digital-on-top P&R methodology; integrate complex digital cores with precision analog blocks.
• Full Backend Execution: drive the digital design through the entire physical pipeline—logic synthesis, DFT/MBIST insertion, MBIST, and routing.
• Physical Optimization & CTS: architect and optimize floorplan, power grid, and CTS; modify RTL to resolve bottlenecks and reduce congestion.
• RTL Design & Architecture: write Verilog/SystemVerilog, design state machines, contribute to top-level architecture with System Architect.
• Timing Closure & Sign-off: own STA, parasitic extraction, and DRC/LVS for digital domains to meet area, power, and high-frequency targets.

Conocimientos

Digital IC design

RTL Verilog/SystemVerilog

Clock tree design

Synthesis/STA

Physical implementation

Herramientas

Cadence Innovus

Cadence Genus

PrimeTime

Calibre

Descripción del empleo

Job Title: Principle Digital IC Design Engineer

Position Type: Full-Time

Location: Santa Clara, CA or Raleigh, NC

Salary Range / Rate: Base$150,000- $300,000 + Bonus & Stock Options

Core Responsibilities:

• Digital-on-Top Flow Development: Establish, own, and execute the complete digital-on-top place and route (P&R) methodology, integrating complex digital control cores with precision analog mixed-signal blocks.
• Full Backend Execution: Drive the digital design through the entire physical pipeline, including logic synthesis, DFT (Design for Test) insertion, MBIST (Memory Built-In Self-Test) implementation, and final routing.
• Physical Optimization & CTS: Architect and optimize the physical floorplan, power grid, and Clock Tree Synthesis (CTS). You will actively modify and optimize the RTL to resolve physical bottlenecks, reduce congestion, and close timing efficiently.
• RTL Design & Architecture: When not in the heavy backend phases of the tape-out cycle, you will operate as a core digital designer—writing Verilog/SystemVerilog, designing state machines, and contributing to the top-level digital architecture alongside the System Architect.
• Timing Closure & Sign-off: Own the Static Timing Analysis (STA), parasitic extraction, and physical verification (DRC/LVS) for the digital domains, ensuring the digital core meets strict area, power, and high-frequency performance targets.

What You Bring (Qualifications):

• Experience: 10+ years of hybrid digital IC design and physical implementation experience, preferably within mixed-signal environments (PMICs, multi-phase controllers, or high-speed data converters).
• EDA Tool Mastery: Deep, hands-on expertise with Cadence physical design and synthesis tools (Innovus/Genus), as well as sign-off tools (PrimeTime, Calibre).
• RTL Fluency: Strong RTL coding skills in Verilog or SystemVerilog. You must be able to read, write, and restructure RTL to achieve optimal physical synthesis.
• Backend Intuition: Proven track record of successfully inserting DFT/MBIST, executing complex clock tree structures, and closing timing on high-speed digital logic in constrained physical areas.
• Ownership Mindset: You are a self-starter who understands the full RTL-to-GDSII pipeline. You communicate clearly with both the architectural math team and the analog layout teams to ensure seamless top-level integration.

About Us:

Founded in 2009, IntelliPro is a global leader in talent acquisition and HR solutions. Our commitment to delivering unparalleled service to clients, fostering employee growth, and building enduring partnerships sets us apart. We continue leading global talent solutions with a dynamic presence in over 160 countries, including the USA, China, Canada, Singapore, Japan, Philippines, UK, India, Netherlands, and the EU.

IntelliPro, a global leader connecting individuals with rewarding employment opportunities, is dedicated to understanding your career aspirations. As an Equal Opportunity Employer, IntelliPro values diversity and does not discriminate based on race, color, religion, sex, sexual orientation, gender identity, national origin, age, genetic information, disability, or any other legally protected group status. Moreover, our Inclusivity Commitment emphasizes embracing candidates of all abilities and ensures that our hiring and interview processes accommodate the needs of all applicants. Learn more about our commitment to diversity and inclusivity at https://intelliprogroup.com/.

Compensation: The pay offered to a successful candidate will be determined by various factors, including education, work experience, location, job responsibilities, certifications, and more. Additionally, IntelliPro provides a comprehensive benefits package, all subject to eligibility.