Senior Digital Design Architect for High-Speed PCIe ASICs

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs seeks Principal Digital Design Engineers to develop micro-architecture and implement front-end circuit designs, including RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. Knowledge of PCIe, Ualink, Esun, Ethernet is essential.

Required: +8 years in complex SoC/silicon for Switch ASIC/Networking/Server. Familiar with Synopsys/Cadence flows and DFT/UVM verification; US work authorization.

Qualifications

• Bachelor's degree in EE required; Master's preferred.
• +8 years' experience in SoC/silicon products for Switch ASIC, Networking, Server/Storage.
• Ability to prioritize and manage multiple tasks, plan for customer meetings, and work with minimal supervision.
• Entrepreneurial, open-mind attitude with customer focus.

Responsibilities

• Develop micro-architecture and implement front-end circuit design (RTL, synthesis, IP integration).
• Perform block-level verification for high-performance network controllers.
• Work with PCIe, Ualink, Esun, Ethernet and related protocols.
• Own end-to-end design from architecture to GDS and drive designs to production.

Skills

High-speed protocols

UVM verification

Silicon bring-up

DFT design

End-to-end ownership

Education

Bachelor's degree in EE

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs seeks Principal Digital Design Engineers to develop micro-architecture and implement front-end circuit designs, including RTL, synthesis, IP integration, and block-level verification for high-performance network controllers. Knowledge of PCIe, Ualink, Esun, Ethernet is essential.

Required: +8 years in complex SoC/silicon for Switch ASIC/Networking/Server. Familiar with Synopsys/Cadence flows and DFT/UVM verification; US work authorization.