Senior Digital Design Engineer — Front-End RTL & High-Speed Protocols

Asteralabs; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Astera Labs in California seeks Digital Design Engineers to develop micro-architecture and front-end circuit design, including RTL, synthesis and IP integration for high-performance network controllers.

The role requires hands-on experience with PCIe, Ualink, Esun, Ethernet and familiarity with Synopsys/Cadence design flows. Bachelor’s in EE is required, Master’s preferred, and US work authorization is required.

Qualifications

• Bachelor’s degree in EE is required; Master’s preferred.
• Strong front-end design and RTL, synthesis experience.
• Experience with PCIe, Ualink, Esun, Ethernet protocols.
• Experience with Synopsys or Cadence tool flows.
• Familiarity with design for test (DFT) and UVM verification.

Responsibilities

• Develop micro-architecture and front-end circuit design, including RTL and synthesis.
• Perform IP integration and block-level verification for high-performance network controllers.
• Collaborate on PCIe/Uplink/Ethernet interfaces and related protocols using standard tool flows.

Skills

RTL design

Synthesis

IP integration

Front-end design

Verilog/VHDL

UVM-based verification

Python scripting

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Synopsys

Cadence

DFT

Job description

Astera Labs in California seeks Digital Design Engineers to develop micro-architecture and front-end circuit design, including RTL, synthesis and IP integration for high-performance network controllers.

The role requires hands-on experience with PCIe, Ualink, Esun, Ethernet and familiarity with Synopsys/Cadence design flows. Bachelor’s in EE is required, Master’s preferred, and US work authorization is required.