Senior Digital Design Engineer Front-End SoC & PCIe

Asteralabs

San Jose (CA)

On-site

USD 140,000 - 200,000

Full time

6 days ago
Be an early applicant
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Job summary

Astera Labs is seeking a Senior Digital Design Engineer in the US to develop the front-end of high-performance network controllers, focusing on RTL, IP integration, and verification. You will collaborate on PCIe, Ualink, Esun, and Ethernet protocols and drive timing closure and DFT for complex SoC designs.

The ideal candidate has 3+ years of experience in Switch ASIC or Networking/Sservers/storage and strong design verification skills, with an ability to work in a fast-paced, customer-focused

Qualifications

  • Bachelor's degree in EE is required; master's preferred.
  • +3 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
  • Ability to prioritize multiple tasks and prepare for customer meetings with minimal supervision.
  • Entrepreneurial, open-minded, can-do attitude with the customer in mind.
  • Authorized to work in the US and start immediately.

Responsibilities

  • Develop front-end micro-architecture and RTL for high-performance network controllers.
  • Integrate IP and perform block-level verification.
  • Work with PCIe, Ualink, Esun, Ethernet protocols.
  • Verify timing closure and DFT; silicon bring-up and debug as needed.

Skills

PCIe & Ethernet protocols
Ualink protocol
Esun protocol
RTL design
Synthesis & timing closure
DFT design
UVM verification
Silicon bring-up
CMOS design (≤28nm)

Education

Bachelor's in Electrical Engineering
Master's degree preferred

Tools

Synopsys tools
Cadence tools

Job description

Astera Labs is seeking a Senior Digital Design Engineer in the US to develop the front-end of high-performance network controllers, focusing on RTL, IP integration, and verification. You will collaborate on PCIe, Ualink, Esun, and Ethernet protocols and drive timing closure and DFT for complex SoC designs.

The ideal candidate has 3+ years of experience in Switch ASIC or Networking/Sservers/storage and strong design verification skills, with an ability to work in a fast-paced, customer-focused

Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Digital Design Lead – PCIe/SoC Frontend
Senior Digital Design Lead – PCIe/SoC Frontend

Astera Labs • San Jose (CA)

On-site
USD 140,000 - 190,000
Flexible time off in the US
Parental leave
401K
+2
Senior Digital Design Engineer: High-Perf Network ASIC
Senior Digital Design Engineer: High-Perf Network ASIC

Astera Labs • San Jose (CA), Northern (KY)

Hybrid
USD 150,000 - 230,000
Senior Digital Design Engineer: Front-End SoC for High-Speed Networks
Senior Digital Design Engineer: Front-End SoC for High-Speed Networks

Astera Labs • San Jose (CA)

On-site
USD 140,000 - 230,000
Senior Digital Design Architect for High-Speed PCIe ASICs
Senior Digital Design Architect for High-Speed PCIe ASICs

Astera Labs • San Jose (CA)

On-site
USD 185,000 - 230,000
Senior Digital Design Engineer — Front-End RTL & High-Speed Protocols
Senior Digital Design Engineer — Front-End RTL & High-Speed Protocols

Asteralabs • San Jose (CA)

On-site
USD 120,000 - 180,000
Senior Digital Design Engineer – High-Speed Network FrontEnd
Senior Digital Design Engineer – High-Speed Network FrontEnd

Astera Labs • San Jose (CA), Northern (KY)

Hybrid
USD 110,000 - 180,000
Restaurant d'entreprise
Senior Digital Design Manager - High-Speed AI Silicon
Senior Digital Design Manager - High-Speed AI Silicon

Astera Labs • San Jose (CA)

On-site
USD 180,000 - 240,000
Flexible time off (US)
Parental leave
401K
+2
Senior Digital Design Lead – PCIe/CXL ASICs
Senior Digital Design Lead – PCIe/CXL ASICs

Astera Labs • San Jose (CA)

On-site
USD 216,000 - 240,000
Discretionary bonus
Tech Lead, Digital Design Engineer New San Jose, California, United States
Tech Lead, Digital Design Engineer New San Jose, California, United States

Astera Labs • San Jose (CA), Northern (KY)

Hybrid
USD 150,000 - 230,000
Digital Design Manager – PCIe/CXL Front-End Lead
Digital Design Manager – PCIe/CXL Front-End Lead

Astera Labs • San Jose (CA)

On-site
USD 216,000 - 240,000