Senior Digital Design Engineer – High-Speed Network SoC

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, California seeks Principal Digital Design Engineers with micro-architecture and front-end circuit design experience to work on high-performance network controllers. You will contribute to RTL, synthesis, IP integration, and block-level verification for PCIe, Ualink, Esun, Ethernet, and related protocols.

The role requires 8+ years in SoC/Silicon, DFT, UVM verification, and ownership from architecture to GDS.

Qualifications

• Strong academic and technical background in electrical engineering with degree in EE.
• 8+ years’ experience in complex SoC/silicon products for Switch ASIC, Networking, Server or Storage.
• Proven ability to own architecture to GDS and drive designs to production.

Responsibilities

• Front-end circuit design including RTL, synthesis, IP integration and block-level verification.
• Owns designs from architecture to GDS and mentors others.
• Work with high-speed protocols such as PCIe, Ualink, Esun and Ethernet.

Skills

PCIe protocol

UVM verification

ASIC/SoC experience

DFT knowledge

CMOS 28nm

Troubleshooting

Education

Bachelor's degree in EE

Master's preferred

Tools

Synopsys tools

Cadence tools

Job description

Astera Labs in San Jose, California seeks Principal Digital Design Engineers with micro-architecture and front-end circuit design experience to work on high-performance network controllers. You will contribute to RTL, synthesis, IP integration, and block-level verification for PCIe, Ualink, Esun, Ethernet, and related protocols.

The role requires 8+ years in SoC/Silicon, DFT, UVM verification, and ownership from architecture to GDS.