Principal Digital Design Engineer – SoC Bring-Up

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs in San Jose, CA, is seeking a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You will own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products.

The role requires leadership in timing closure, DFT features, and production-grade CMOS design for servers and data-center

Qualifications

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Experience with high-speed protocols and third-party IP integration.
• Production experience with CMOS nodes ≤7nm.

Responsibilities

• Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design.
• Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues.
• Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance.
• Work closely with post-silicon teams to facilitate silicon bring-up and debug.
• Mentor junior engineers to develop their technical skills and expertise.
• Actively contribute to the development and improvement of silicon development processes.
• Drive designs to production, ensuring accountability for quality, schedule, and overall design success.

Skills

Architecture definition

RTL coding

Timing closure

DFT implementation

Test & verification collaboration

Education

Bachelor’s degree in electrical engineering or equivalent

Tools

Cadence flows

Synopsys flows

UVM verification

Job description

Astera Labs in San Jose, CA, is seeking a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You will own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high-performance products.

The role requires leadership in timing closure, DFT features, and production-grade CMOS design for servers and data-center