Senior Digital ASIC Design Engineer - High-Speed SoCs

Teradyne; Agoura Hills (CA); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Teradyne seeks a Senior ASIC Digital Design Engineer in Agoura Hills, CA to develop complex mixed-signal ASICs for next‑generation semiconductor test systems. You will work with architects, analog designers, verification, and physical design teams, driving digital design from architecture to silicon bring‑up.

You will own critical subsystems, influence technical direction, and mentor junior engineers, leveraging strong Verilog RTL expertise and robust collaboration across cross‑functional teams.

Qualifications

• 8+ years of ASIC or digital design experience with VerilogRTL development.
• Experience designing complex digital blocks (state machines, FIFOs, high-speed datapaths).
• Knowledge of synthesis, STA, CDC, timing closure.

Responsibilities

• Drive digital design activities from architecture definition through silicon bring-up.
• Own critical ASIC subsystems and influence technical direction.
• Collaborate with architects, analog, verification, and physical design teams.

Skills

Verilog RTL

Digital design

RTL to Netlist

Scripting (Python/Tcl)

Education

BSEE

MSEE or PhD

Tools

SoC integration

Job description

Teradyne seeks a Senior ASIC Digital Design Engineer in Agoura Hills, CA to develop complex mixed-signal ASICs for next‑generation semiconductor test systems. You will work with architects, analog designers, verification, and physical design teams, driving digital design from architecture to silicon bring‑up.

You will own critical subsystems, influence technical direction, and mentor junior engineers, leveraging strong Verilog RTL expertise and robust collaboration across cross‑functional teams.