Senior ASIC Lead & Program Director

Teradyne

Agoura Hills (CA)

On-site

USD 192,000 - 308,000

Full time

14 days+
Application generator

An application made for this job — a tailored resume and cover letter that speak straight to the posting.

Get past ATS filters

Benefits offered by this job

Medical
Dental
Vision
Flexible Spending Accounts
Retirement plans
Life and disability insurance
Paid vacation & holidays
Tuition assistance

Job summary

Teradyne, located in Agoura Hills, CA, seeks a Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment systems.

This role requires a proven leader who can coordinate architecture, analog/digital design, verification, physical design, and production teams, while ensuring on-time, on-budget delivery. Strong program management and external partner collaboration are essential.

Qualifications

  • BSEE, MSEE, or equivalent with 15+ years in semiconductor industry.
  • 5+ years leading complex ASIC developments.
  • Experience managing geographically distributed teams and external partners.
  • Strong program management including schedule, risk, and executive communications.
  • Experience with advanced-node ASIC development preferred.

Responsibilities

  • Accountable for successful ASIC execution from concept through production.
  • Lead cross-functional teams across architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
  • Define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
  • Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
  • Conduct regular program reviews and provide status updates to engineering and executive leadership.
  • Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
  • Resolve technical and program conflicts while balancing quality, cost, and schedule objectives.
  • Drive tapeout readiness reviews and silicon bring-up planning.
  • Develop staffing plans and identify resource gaps throughout the project lifecycle.

Skills

Led complex ASIC developments
Cross-functional leadership
Program management
Advanced-node ASIC development

Education

BSEE, MSEE, or equivalent

Tools

EDA tools
IP suppliers
Foundry partners

Job description

Teradyne, located in Agoura Hills, CA, seeks a Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment systems.

This role requires a proven leader who can coordinate architecture, analog/digital design, verification, physical design, and production teams, while ensuring on-time, on-budget delivery. Strong program management and external partner collaboration are essential.

Get your free, confidential resume review.
or drag and drop your file here.
Similar jobs

Similar jobs worth comparing

Senior ASIC Chip Lead - Cross-Functional Tapeout Champion
Senior ASIC Chip Lead - Cross-Functional Tapeout Champion

Teradyne • Agoura Hills (CA)

On-site
USD 192,000 - 308,000
medical
dental
vision
+6
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)
Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 192,000 - 308,000
medical
dental
vision
+6
Senior ASIC Chip Lead / Project Lead
Senior ASIC Chip Lead / Project Lead

Teradyne • Agoura Hills (CA)

On-site
USD 192,000 - 308,000
Medical
Dental
Vision
+5
Senior Digital ASIC Design Engineer - High-Speed SoCs
Senior Digital ASIC Design Engineer - High-Speed SoCs

Teradyne • Agoura Hills (CA)

On-site
USD 155,000 - 248,000
Discretionary bonus
Senior ASIC Bench Characterization Lead
Senior ASIC Bench Characterization Lead

Teradyne • Agoura Hills (CA), Northern (KY)

Hybrid
USD 165,000 - 265,000
Discretionary bonus
Comprehensive benefits package
Senior ASIC Chip Lead & Architect
Senior ASIC Chip Lead & Architect

AMD • San Jose (CA)

On-site
USD 180,000 - 250,000
Chip Lead - Senior ASIC Architect & Program Leader
Chip Lead - Senior ASIC Architect & Program Leader

Advanced Micro Devices • San Jose (CA)

On-site
USD 180,000 - 220,000
Senior ASIC Verification Lead - SystemVerilog/UVM
Senior ASIC Verification Lead - SystemVerilog/UVM

Teradyne • Reading (MA)

Hybrid
USD 155,000 - 308,000
Discretionary bonus eligibility
Comprehensive benefits
Salary range competitiveness
Sr. Digital ASIC Design Engineer (TERADYNE, Agoura Hills, CA)
Sr. Digital ASIC Design Engineer (TERADYNE, Agoura Hills, CA)

Teradyne • Agoura Hills (CA)

On-site
USD 155,000 - 248,000
Discretionary bonus
Lead FPGA & ASIC Design Manager, Compute Test
Lead FPGA & ASIC Design Manager, Compute Test

Teradyne • North Reading (MA)

On-site
USD 156,000 - 249,000
Health benefits
Tuition assistance
Paid vacation