Senior Analog IC Design Engineer – High-Speed Mixed-Signal

Teradyne; Agoura Hills (CA); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health benefits

Discretionary bonus plan

Job summary

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Senior Analog Design Engineer to design mixed-signal ICs for ATE instruments. You will develop circuit specifications and conceive architectures that meet performance goals across process and operating conditions.

The role requires a BSEE with 8+ years of experience in high-frequency analog/mixed-signal IC design, expertise in VCOs/PLLs/DLLs/ADCs/DACs, and proficiency in Verilog/Verilog-A.

Qualifications

• BSEE required; MSEE or PhD preferred.
• 8+ years of experience in design and characterization of high-frequency mixed-signal ICs.
• Strong knowledge of high-frequency analog mixed-signal design and physical design.
• Experience with VCOs, PLLs, DLLs, ADCs, DACs, clock and data recovery, broadband amplifiers, bias generators, clock distribution networks, high-frequency I/Os, high-frequency CML designs, high voltage.
• Proficiency in Verilog or Verilog-A modeling.
• Cadence Skill or Ocean scripting experience is a plus.
• Experience with ATE test development is a plus.

Responsibilities

• Develop detailed circuit specifications for mixed signal circuits.
• Conceive circuit architectures and transistor-level topologies that satisfy performance.
• Physical implementation (layout) of high speed circuits, directly or with assistance.
• Optimize circuits via simulation with Cadence over process and operating conditions.
• Integration of circuit elements into large analog/mixed-signal ASICs.
• Participation in the characterization of ASIC circuits.

Skills

High-frequency mixed-signal IC design

Verilog/Verilog-A modeling

Mentorship / leading small teams

Layout and physical design

CMOS/BiCMOS knowledge

Education

BSEE

MSEE or PhD in Electrical Engineering

Tools

Cadence EDA tools

Cadence Skill

Ocean scripting

Job description

Teradyne’s Semiconductor Test Division in Agoura Hills, CA is seeking a Senior Analog Design Engineer to design mixed-signal ICs for ATE instruments. You will develop circuit specifications and conceive architectures that meet performance goals across process and operating conditions.

The role requires a BSEE with 8+ years of experience in high-frequency analog/mixed-signal IC design, expertise in VCOs/PLLs/DLLs/ADCs/DACs, and proficiency in Verilog/Verilog-A.