Senior ASIC Chip Lead / Project Lead (TERADYNE, Agoura Hills, CA)

Teradyne Inc.; Agoura Hills (CA); On-site; USD 192,000 - 308,000; Full time

Benefits offered by this job

medical

dental

vision

Flexible Spending Accounts

retirement savings plans

life and disability insurance

paid vacation & holidays

tuition assistance programs

and more

Job summary

Teradyne’s Silicon Technology Engineering team seeks an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems.

This role requires a proven leader who can coordinate cross-functional engineering teams, external partners, and key stakeholders while ensuring technical, schedule, cost, and quality objectives are met.

Qualifications

• BSEE, MSEE, or equivalent with 15+ years of semiconductor industry experience and 5+ years leading complex ASIC developments.
• Proven success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.
• Experience managing geographically distributed teams and external design partners.
• Strong program management skills, including schedule planning, risk management, and executive communications.
• Proven ability to lead through influence across multiple engineering disciplines.
• Experience with advanced-node ASIC development preferred.

Responsibilities

• Accountable for successful ASIC execution from concept through production, including schedule, quality, cost, tapeout readiness, and first-pass silicon success.
• Lead cross-functional teams including architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
• Partner with system architects and engineering leaders to define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
• Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
• Conduct regular program reviews and provide status updates to engineering and executive leadership.
• Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
• Resolve technical and program conflicts while balancing quality, cost, and schedule objectives.
• Drive tapeout readiness reviews and silicon bring-up planning.
• Develop staffing plans and identify resource gaps throughout the project lifecycle.

Skills

ASIC leadership

Program management

Cross-functional leadership

Stakeholder communication

Education

BSEE, MSEE, or equivalent

Tools

EDA tools

Job description

We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world!

We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive.

Our Purpose

TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day.

Opportunity Overview

Teradyne's Silicon Technology Engineering team is seeking an experienced Senior ASIC Chip Lead / Project Lead to drive the development and delivery of a large-scale mixed-signal ASIC for next-generation Automated Test Equipment (ATE) systems.

This role requires a proven leader who can drive complex ASIC programs from concept through production, coordinating cross-functional engineering teams, external partners, and key stakeholders while ensuring successful execution against technical, schedule, cost, and quality objectives.

Depending on experience and project needs, the successful candidate may serve as the ASIC Chip Lead, owning technical execution, or as the Project Lead, owning overall program execution, or both.

The ideal candidate combines strong technical depth with exceptional program leadership and has a proven track record delivering complex ASICs involving multiple internal teams, external vendors, and foundry partners.

• Accountable for successful ASIC execution from concept through production, including schedule, quality, cost, tapeout readiness, and first-pass silicon success.
• Lead cross-functional teams including architecture, analog design, digital design, verification, physical design, package engineering, test, characterization, and operations.
• Partner with system architects and engineering leaders to define ASIC architecture, technical tradeoffs, execution strategy, and product requirements.
• Drive schedule development, critical-path management, milestone tracking, and risk mitigation.
• Conduct regular program reviews and provide status updates to engineering and executive leadership.
• Coordinate outsourced design partners, EDA vendors, IP suppliers, and foundry partners.
• Resolve technical and program conflicts while balancing quality, cost, and schedule objectives.
• Drive tapeout readiness reviews and silicon bring-up planning.
• Develop staffing plans and identify resource gaps throughout the project lifecycle.

All About You

We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you’re ready to join us in this mission, take a closer look at the minimum criteria for the position.

• BSEE, MSEE, or equivalent with 15+ years of semiconductor industry experience and 5+ years leading complex ASIC developments.
• Demonstrated success leading multiple complex mixed-signal ASICs through architecture, design, verification, tapeout, silicon bring-up, and production.
• Experience managing geographically distributed teams and external design partners.
• Strong program management skills, including schedule planning, risk management, and executive communications.
• Proven ability to lead through influence across multiple engineering disciplines.
• Experience with advanced-node ASIC development preferred.

Compensation

The base salary range for this role is $192,300-$307,600. This range is a good faith estimate, and the amount of base salary will correspond with experience and skill set. This range can also fluctuate depending on demand and location.

Incentive Plan

This job is eligible for discretionary bonus(es) based on financial performance.

Benefits

Teradyne offers a variety of robust health and well-being benefit programs, including medical, dental, vision, Flexible Spending Accounts, retirement savings plans, life and disability insurance, paid vacation & holidays, tuition assistance programs, and more.

• medical
• dental
• vision
• Flexible Spending Accounts
• retirement savings plans
• life and disability insurance
• paid vacation & holidays
• tuition assistance programs
• and more

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