Senior Digital ASIC Designer – High‑Performance Hardware

Draper; Boston (MA); On-site; USD 82,300 - 220,000; Full time

Benefits offered by this job

Workplace flexibility

Discounts to local museums and culture

Job summary

Draper Laboratory is seeking a Senior Digital ASIC Designer to develop high-performance digital ASICs from RTL through synthesis. You will work in multidisciplinary teams on projects across application areas and contribute to design-for-test as well as layout considerations.

The role requires 7–10 years of ASIC hardware experience (or 5–10 with a Master’s), expertise in front-end design, SystemVerilog, and proficiency with Cadence or Synopsys toolchains. U.S.

Qualifications

• Requires 7-10 years of experience with a bachelor’s degree, or 5-10 years with a master’s degree in ASIC Hardware Engineering or related.
• Front-end digital systems design with Cadence or Synopsys.
• Fluent in SystemVerilog, Verilog or VHDL; familiar with LINT, simulation and synthesis.

Responsibilities

• Design and simulate circuits at transistor level to meet architecture requirements.
• Contribute to system-level design and optimize hardware for performance, power, and cost.
• Drive complex chip architectures and lead design teams.

Skills

IC design

ASIC design

SystemVerilog

Verilog/VHDL

Architectural design

Problem solving

Team leadership

Communication

Power/performance optimization

Education

Bachelor’s degree in Engineering

Master’s degree preferred

Tools

Cadence

Synopsys

Job description

Draper Laboratory is seeking a Senior Digital ASIC Designer to develop high-performance digital ASICs from RTL through synthesis. You will work in multidisciplinary teams on projects across application areas and contribute to design-for-test as well as layout considerations.

The role requires 7–10 years of ASIC hardware experience (or 5–10 with a Master’s), expertise in front-end design, SystemVerilog, and proficiency with Cadence or Synopsys toolchains. U.S.