Senior RTL Digital Design Engineer – ASIC & SoC Innovator

Teradyne; North Reading (MA); On-site; USD 192,000 - 308,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision care

Retirement savings plan

Paid vacation

Job summary

Teradyne, North Reading, MA, is seeking a Senior RTL Digital Design Engineer to drive complex mixed-signal ASIC development. You will work with architects, analog and verification teams to define architecture and steer digital design through silicon bring-up.

The role offers ownership of critical digital subsystems, collaboration across disciplines, and leadership opportunities to guide technical direction in a highly integrated environment.

Qualifications

• 8+ years of ASIC or digital design experience with Verilog/SystemVerilog RTL development.
• Experience designing complex digital blocks including state machines, FIFOs, high-speed datapaths, arbitration.
• Strong knowledge of ASIC development flows including synthesis, static timing analysis (STA), clock domain crossing (CDC), and timing closure.
• Experience integrating third-party and custom IP into large-scale SoCs or mixed-signal ASICs.
• Proficiency with scripting and automation using Python, Tcl, Make, or similar languages.
• Experience supporting verification, silicon bring-up, debugging, and root-cause analysis.
• Strong collaboration, communication, and problem-solving skills with the ability to mentor junior engineers and drive technical excellence across cross-functional teams.

Responsibilities

• Own critical ASIC subsystems from architecture definition through silicon bring-up.
• Collaborate with architects, analog designers, verification engineers, and physical design teams to drive design activities.
• Mentor junior engineers and contribute to technical direction across cross-functional teams.

Skills

Verilog/SystemVerilog

ASIC design

RTL patterns

Synthesis/STA/CDC

IP integration

Python scripting

Debugging

Cross-functional

Education

BSEE

MS EE or PhD desired

Tools

Python

Tcl

Make

Job description

Teradyne, North Reading, MA, is seeking a Senior RTL Digital Design Engineer to drive complex mixed-signal ASIC development. You will work with architects, analog and verification teams to define architecture and steer digital design through silicon bring-up.

The role offers ownership of critical digital subsystems, collaboration across disciplines, and leadership opportunities to guide technical direction in a highly integrated environment.