RTL Design Engineer - Next-Gen Mixed-Signal ASICs

Teradyne; Reading (MA); On-site; USD 123,000 - 197,000; Full time

Benefits offered by this job

Health and well-being benefits

Medical, dental, vision coverage

Flexible Spending Accounts

Retirement savings plans

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne in North Reading, MA, seeks an experienced RTL Designer to join the Silicon Technology Engineering group. You will contribute to advanced node ASIC development, collaborating with Analog and architecture teams across specification, design, verification, physical design, and silicon bring-up.

The role emphasizes high-speed memory, timing closure, and automation via scripting. Minimum 5+ years in EE with Verilog RTL, CDC/STA, and memory/serial interfaces; strong collaboration with

Qualifications

• BSEE or MSEE in Electrical Engineering with 5+ years of experience.
• Extensive logic design experience writing RTL in Verilog.
• Design of state machines, FIFOs, high speed data paths and arbitration logic and DFT.
• Experience with logic synthesis and timing constraints.
• Experience with clock domain crossings (CDC) and static timing analysis (STA).
• Experience with high speed memory and serial interfaces.
• Experience with automation through scripting such as Python, Tcl & Make.

Responsibilities

• Develop specifications, micro-architecture, and RTL design for mission-critical blocks with the chip architect.
• Integrate industry standard and Teradyne IPs.
• Collaborate with verification on test plans, debug, and coverage closure.
• Provide timing constraints and STA support to the Physical Design team through timing closure.
• Provide post-silicon lab bring-up and debug support.

Skills

Verilog RTL design

State machines & FIFOs

Synthesis & timing

CDC & STA

High-speed memory/serial

Scripting (Python/Tcl/Make)

Education

BSEE or MSEE in Electrical Engineering

Job description

Teradyne in North Reading, MA, seeks an experienced RTL Designer to join the Silicon Technology Engineering group. You will contribute to advanced node ASIC development, collaborating with Analog and architecture teams across specification, design, verification, physical design, and silicon bring-up.

The role emphasizes high-speed memory, timing closure, and automation via scripting. Minimum 5+ years in EE with Verilog RTL, CDC/STA, and memory/serial interfaces; strong collaboration with