Senior DFX/SLM Architect for ASICs

Ericsson AB; Austin (TX); Híbrido; USD 180.000 - 260.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Health benefits

401(k) plan with company match

Paid time off and holidays

Parental leave and work-life balance

Descripción de la vacante

Ericsson seeks a Senior DFX Lead for ASIC development in Austin, TX. You will own DFX/SLM architecture, drive the full DFX stack, and partner with physical design for timing sign-off. You’ll integrate DFX into RTL and lead RTL/gate-level verification across the program.

You will mentor engineers, coordinate with teams in Austin, Sweden, and partners, and shape lifecycle features through tap-out to field operations. This role supports hybrid on-site work in Austin.

Formación

• 12+ years in SoC, IP, or ASIC design with emphasis on DFX
• Minimum BSEE; MSEE preferred
• Expert hands-on command of the DFX stack (scan, compression, ATPG, JTAG, boundary scan)
• Post-silicon bring-up, yield learning, test-time reduction experience
• RTL/Verilog/SystemVerilog, synthesis, STA, clock/reset, and physical-design timing-closure familiarity

Responsabilidades

• Own DFX and SLM architecture for one or more ASIC programs and sign off DFX/SLM scope before tape-out
• Architect and drive the full DFX/SLM stack including scan, ATPG, memory/logic BIST, JTAG, and boundary scan
• Integrate DFX into RTL at IP/SoC level and own DFX timing constraints
• Own DFX/SLM verification across RTL and gate-level tests, including fault logging and in-field tests
• Deliver test content, patterns, and coverage closure; review test quality against targets
• Define on-die debug/observability and lead bring-up, yield learning and fault analysis
• Shape SLM architecture with cross-functional teams and automate DFX flows for scale
• Lead and grow the DFX engineers, mentoring and coordinating across Austin, Sweden, and partner sites

Conocimientos

DFX stack expertise

ASIC/SoC design experience

RTL (Verilog/SystemVerilog)

JTAG/IJTAG boundary scan

DFX verification

Leadership/mentorship

Cross-site communication

Educación

Bachelor's degree in EE

MSEE preferred

Herramientas

IEEE 1149.1/1149.6/1687 boundary scan tooling

Memory/Logic BIST tooling

Descripción del empleo

Ericsson seeks a Senior DFX Lead for ASIC development in Austin, TX. You will own DFX/SLM architecture, drive the full DFX stack, and partner with physical design for timing sign-off. You’ll integrate DFX into RTL and lead RTL/gate-level verification across the program.

You will mentor engineers, coordinate with teams in Austin, Sweden, and partners, and shape lifecycle features through tap-out to field operations. This role supports hybrid on-site work in Austin.