Senior ASIC Verification Engineer - 5G IP (Hybrid)

Ericsson; Austin (TX); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Ericsson is seeking an ASIC Design Verification Engineer in Austin, TX, to own full verification across IP/ASIC/SoC with hands-on SystemVerilog/UVM. You’ll design testbenches from the ground up, debug RTL, and verify blocks to chip level while coordinating with hardware and embedded software teams in a hybrid work environment.

The role emphasizes architecture of verification environments, breaking and fixing critical bugs, and delivering measurable coverage closures within a fast-moving team.

Qualifications

• Several years of hands-on, in industry RTL verification experience in IP, ASIC, SoC.
• Deep, practical experience with SystemVerilog and UVM.
• Proven ability to architect and build testbenches from the ground up.
• Block- and/or top-level RTL debug experience — you know how to find what's hiding in the waveform.
• IP familiarity in one or more of: SerDes, PCIe, ARM Subsystems, DSPs/Accelerators, or Ethernet.
• Scripting proficiency — TCL, Python, Perl, or equivalent.
• Clear, confident communicator — you can explain what you found and why it matters.

Responsibilities

• Take on real ownership across the full verification stack.
• Dig into TLM modeling for early architectural verification.
• Own block- and top-level ASIC/IP verification and coverage closure.
• Design and build UVM environments from scratch.
• Bridge hardware and embedded software to verify real-world behavior.

Skills

SystemVerilog

UVM

Testbench architecture

RTL debug

Scripting TCL/Python

IP/SoC verification

Communication skills

Education

Bachelor's degree in Electrical Engineering or Computer Engineering

Tools

AMBA AXI/ACE-Lite/CHI

Linux/GIT/LSF

PCIe/SerDes experience

Job description

Ericsson is seeking an ASIC Design Verification Engineer in Austin, TX, to own full verification across IP/ASIC/SoC with hands-on SystemVerilog/UVM. You’ll design testbenches from the ground up, debug RTL, and verify blocks to chip level while coordinating with hardware and embedded software teams in a hybrid work environment.

The role emphasizes architecture of verification environments, breaking and fixing critical bugs, and delivering measurable coverage closures within a fast-moving team.