Senior ASIC IP Verification Engineer | 5G Infrastructure

Ericsson AB; Austin (TX); Hybrid; USD 130,000 - 190,000; Full time

Job summary

Ericsson in Austin, TX seeks an experienced Senior Design Verification Engineer for ASIC IP. The role spans block- and top-level verification, UVM testbench creation, and HW/SW verification integration.

Hybrid on-site work combines leadership with hands-on RTL challenges in a live 5G infrastructure context. You will lead verification efforts across the stack, mentor colleagues, and drive architecture decisions while collaborating with SerDes, PCIe, ARM subsystems, and AMBA-related interfaces.

Qualifications

• Several years of RTL verification in an industrial setting.
• Strong SystemVerilog/UVM proficiency with architectural ownership.
• Experience building testbenches from scratch.
• Familiarity with SerDes, PCIe, ARM subsystems, DSPs/accelerators or Ethernet.
• Scripting in TCL, Python, Perl or equivalent.

Responsibilities

• Own block- and top-level verification and sign-off.
• Design and build UVM testbenches from scratch.
• Develop verification environments spanning the full stack.
• Mentor engineers and influence verification methodology.

Skills

RTL verification

SystemVerilog/UVM

Testbench design

Team leadership

Scripting TCL/Python

Education

B.S. or M.S. in Electrical/Computer Engineering

Tools

Linux

GIT

LSF

Job description

Ericsson in Austin, TX seeks an experienced Senior Design Verification Engineer for ASIC IP. The role spans block- and top-level verification, UVM testbench creation, and HW/SW verification integration.

Hybrid on-site work combines leadership with hands-on RTL challenges in a live 5G infrastructure context. You will lead verification efforts across the stack, mentor colleagues, and drive architecture decisions while collaborating with SerDes, PCIe, ARM subsystems, and AMBA-related interfaces.