Senior FPGA Architect: Austin with Relocation Support

Confident Search Consultants; Austin (TX); On-site; USD 150,000 - 180,000; Full time

Benefits offered by this job

Relocation assistance

Visa sponsorship (US Citizenship or GC

Job summary

Confident Search Consultants in Austin, TX is seeking a Senior FPGA Engineer to own the FPGA development lifecycle for advanced embedded computing products. You will translate system and customer requirements into robust FPGA architectures and lead implementation and verification with hardware and software teams.

You will work across LVDS, JESD204B/C, RFSoC, DDR interfaces and timing closure, applying Vivado and other toolchains.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 7+ years FPGA design and development experience.
• Experience interfacing FPGAs with RF converters using LVDS, JESD204B/C, or RFSoC.
• Hands-on experience with Vivado and high-speed FPGA design; strong VHDL and Verilog/SystemVerilog knowledge.

Responsibilities

• Own the FPGA development lifecycle from architecture and requirements through implementation, simulation, verification, and hardware validation.
• Translate system and customer requirements into robust FPGA architectures and lead implementation and verification.
• Collaborate with hardware and software teams to deliver reliable embedded computing products.

Skills

FPGA design

VHDL/Verilog

High-speed digital design

Python / C / C++

Embedded Linux

Technical leadership

Education

Bachelor’s degree in Electrical Engineering or Computer Engineering

Tools

AMD/Xilinx Vivado

Vivado Simulator

ILAs (Integrated Logic Analyzers)

ModelSim/QuestaSim

Job description

Confident Search Consultants in Austin, TX is seeking a Senior FPGA Engineer to own the FPGA development lifecycle for advanced embedded computing products. You will translate system and customer requirements into robust FPGA architectures and lead implementation and verification with hardware and software teams.

You will work across LVDS, JESD204B/C, RFSoC, DDR interfaces and timing closure, applying Vivado and other toolchains.