DFX Lead Engineeer

Ericsson AB; Austin (TX); Hybrid; USD 180,000 - 260,000; Full time

Benefits offered by this job

Health benefits

401(k) plan with company match

Paid time off and holidays

Parental leave and work-life balance

Job summary

Ericsson seeks a Senior DFX Lead for ASIC development in Austin, TX. You will own DFX/SLM architecture, drive the full DFX stack, and partner with physical design for timing sign-off. You’ll integrate DFX into RTL and lead RTL/gate-level verification across the program.

You will mentor engineers, coordinate with teams in Austin, Sweden, and partners, and shape lifecycle features through tap-out to field operations. This role supports hybrid on-site work in Austin.

Qualifications

• 12+ years in SoC, IP, or ASIC design with emphasis on DFX
• Minimum BSEE; MSEE preferred
• Expert hands-on command of the DFX stack (scan, compression, ATPG, JTAG, boundary scan)
• Post-silicon bring-up, yield learning, test-time reduction experience
• RTL/Verilog/SystemVerilog, synthesis, STA, clock/reset, and physical-design timing-closure familiarity

Responsibilities

• Own DFX and SLM architecture for one or more ASIC programs and sign off DFX/SLM scope before tape-out
• Architect and drive the full DFX/SLM stack including scan, ATPG, memory/logic BIST, JTAG, and boundary scan
• Integrate DFX into RTL at IP/SoC level and own DFX timing constraints
• Own DFX/SLM verification across RTL and gate-level tests, including fault logging and in-field tests
• Deliver test content, patterns, and coverage closure; review test quality against targets
• Define on-die debug/observability and lead bring-up, yield learning and fault analysis
• Shape SLM architecture with cross-functional teams and automate DFX flows for scale
• Lead and grow the DFX engineers, mentoring and coordinating across Austin, Sweden, and partner sites

Skills

DFX stack expertise

ASIC/SoC design experience

RTL (Verilog/SystemVerilog)

JTAG/IJTAG boundary scan

DFX verification

Leadership/mentorship

Cross-site communication

Education

Bachelor's degree in EE

MSEE preferred

Tools

IEEE 1149.1/1149.6/1687 boundary scan tooling

Memory/Logic BIST tooling

Job description

Grow with us

About this opportunity

Senior DFX Lead Ericsson Silicon | ASIC Development

Location: Austin, Texas Hybrid, On-Site work schedule

Ericsson's Radio and Baseband products run on ASICs we design ourselves, at the most advanced process nodes, and every silicon must be testable, debuggable, and observable throughout its life in the field. The Austin DFX & SLM team owns that capability for every ASIC across Ericsson's product line - DFX, Silicon Lifecycle Management (SLM) and Reliability, Availability and Serviceability (RAS) - from requirements and architecture through IP and SoC integration to silicon bring-up and in-field operation. The team holds tape-out gate authority for DFX and SLM scope on every program.

What you will do

• Own DFX and SLM architecture for one or more ASIC programs: the DFT plan, the test strategy, and the RAS requirements (fault detection, isolation and logging; in-field self-test; self-healing and repair; event routing from chip to board). Sign off DFX and SLM scope as a precondition for tape-out.
• Architect and drive the full DFX/SLM stack: scan and compression, ATPG, memory and logic BIST (with memory repair), JTAG/IJTAG and boundary scan (IEEE 1149.1, 1149.6, 1687), in-field test, and test access for custom, analog, and high-speed IP.
• Integrate DFX into RTL at IP and SoC level, own DFX timing constraints (SDC), and partner with physical design on implementation and timing sign-off.
• Own DFX/SLM verification: define and execute RTL and gate-level verification of the DFT, debug, and lifecycle-monitoring infrastructure across production-test and in-field use cases, including DFT rule checks and equivalence checking.
• Deliver test content to test engineering and silicon partners: pattern generation, fault simulation, coverage closure (structural, at-speed, functional) and test-time optimization; review test quality against DPPM targets with ASIC vendors.
• Define on-die debug and observability (scan/array dump, register-state snapshot on functional fail) and lead the design side of bring-up, yield learning and failure analysis, closing the loop into the next tape-out.
• Shape the SLM architecture with the SLM team and enable the runtime applications built on it (in-field monitoring, diagnostics, telemetry, adaptive power tuning) with systems, firmware and software teams - so lifecycle features are designed in at chip-spec time, not bolted on later.
• Advance the methodology: work with EDA vendors and CAD to define next-generation DFT flows and automate the DFX execution pipeline, so it scales across programs.
• Lead and grow the team: mentor DFX engineers, review their work, and represent DFX to architects, program management, and external partners across Austin, Sweden, and partner sites.

Join our Team

What you will bring

• 12+ years in SoC, IP, or ASIC design with an emphasis on DFX (DFT, DFD, DFM), including several years leading DFX on a complex SoC through tape-out on advanced process nodes.
• Minimum BSEE; MSEE preferred.
• Expert, hands-on command of the DFX stack - scan and compression, ATPG, JTAG/IJTAG, boundary scan, memory and logic BIST - and the trade-offs between test quality, test time and area, and their impact on implementation.
• Hands-on experience with a production DFT flow.
• Proven ownership of SoC-level DFT planning, architecture and execution, and of DFX verification (memory BIST, JTAG, boundary scan, in-field tests, custom IP test interfaces).
• Post-silicon experience: bring-up, yield learning, test-time reduction, and pattern delivery, working closely with test and product engineering.
• Working knowledge of RTL (Verilog/SystemVerilog), synthesis, STA and clock/reset design, and of physical-design and timing-closure flows so DFT integrates cleanly.
• Ability to lead through influence: set direction, review others’ work, and be the DFX voice to architects, program management, and external partners, with clear written and spoken communication across sites and time zones.

Nice to have

• RAS and SLM depth: on-die sensors and monitors, fault logging, telemetry, in-field diagnostics, and the firmware/SDK that reads them.
• DFT for chiplet, 2.5D or 3D designs (e.g., IEEE 1838).
• System-level test (SLT) methodology and functional ATE pattern enablement.
• Functional-safety or RAS experience on high-reliability products.
• Experience partnering with external ASIC vendors on DFT, test content and test quality.
• Background in wireless infrastructure, networking or compute ASICs.

Why join Ericsson

Your work ends up in networks that connect billions of people - and you see your designs through from requirements to working silicon in the lab, in production test, and in the field for years afterward. You will own DFX, RAS, and SLM architecture that is reused across every ASIC in the product line, working beside engineers who built this capability from the ground up, in a global team with a speak‑up culture and a real commitment to work‑life balance.

Diversity and inclusion are core to our values, and collaboration across different experiences drives the innovation essential to our growth.

Ericsson is proud to be an Equal Opportunity Employer.

We encourage people from all backgrounds to apply and realize their full potential as part of our Ericsson team.

If you need assistance or to request an accommodation due to a disability, please contact Ericsson at [e-mail].

DISCLAIMER: The above statements are intended to describe the general nature and level of work being performed by employees in this position. They are not an exhaustive list of all responsibilities, duties and skills required for this position, and you may be required to perform additional job tasks as assigned.

Primary country and city: USA || Austin, Texas

Job details: Developer

Compensation and Benefits at Ericsson

At Ericsson, we know that our people are the key to our success. We offer a competitive package to help with your individual needs and goals.

Your Pay

The salary range for this position is dependent on various factors including, but not limited to, location, and the candidate’s combination of job‑related knowledge, qualifications, skills, education, training, and experience.

Short-Term Variable Compensation Plan:

Your pay also includes the opportunity for an annual bonus. Actual bonus payouts are based on performance of the business against the unit’s objectives, individual performance, and the individual bonus target. Certain eligibility and pro‑ration rules apply.

Your Health

Ericsson offers excellent health benefits including the choice of three medical plan options and a dental plan option that allow an employee to select the level of coverage that suits their needs. Employees will receive company credits in an amount equal to the cost that Ericsson pays toward the cost of their medical and dental premiums for themselves and eligible covered dependents.

Your Financial Security

We invest in both your short and long‑term financial wellbeing. The Ericsson US 401(k) Plan offers an automatic 3% company contribution and Ericsson match $1 for every $1 you put into the 401(k) Plan on the first 3% of your eligible pay, plus 50 cents on every $1 on the next 2% of eligible pay. When you contribute at least 5% of eligible pay, you are receiving Ericsson’s full matching contributions of 4%. Matching and company automatic contributions stop when your total eligible pay for the year reaches the IRS limits. Employees will also receive company credits in an amount equal to the cost of basic life insurance and basic accidental death and dismemberment coverage, as well as short-term and long-term disability coverage. Employees also have the option to participate in Ericsson’s Stock Purchase Plan.

Your Time

Your work-life balance is important to us. New employees are provided a minimum of 15 days of accrued vacation, up to 3 personal days per year, 11 annual holidays, 8 hours of volunteer time, and 80 hours of sick time annually. Please note paid time off is pro‑rated based on the employee’s start date. Furthermore, Ericsson provides up to 16 weeks of paid maternity leave and 6 weeks of parental or adoption leave at 100% of pay.

Additional Benefits

Ericsson offers many other company-paid benefits such as financial wellness programs, educational assistance, matching gifts, and recognition programs.