Senior DFx Methodology Architect - SoC Test & Yield

Advanced Micro Devices; San Jose (CA); Hybrid; USD 160,000 - 210,000; Full time

Job summary

Advanced Micro Devices in California seeks a DFx engineer to define constraints for IPs, optimize timing, PnR and DFx methodologies across next‑gen monolithic and stacked SoCs. You will collaborate with IP teams to ensure testability, debug, characterization, repair and yield improvements.

The role requires strong analytical skills, RTL design/verification experience, and familiarity with DFx concepts. Hybrid work options near San Jose are available.

Qualifications

• RTL design, timing constraints, and design methodologies are required.
• Experience with STA, RTL-DRC, CDC, RDC, and constraints checking.
• Programming experience in Perl, TCL, Python is preferred.
• Design verification using Verilog simulations, coverage analysis, and assertions is expected.
• Knowledge of Scan design, ATPG, Memory BIST, repair and yield improvements is a plus.

Responsibilities

• Define constraints and dependencies for IPs based on block interfaces, power supply & configuration requirements.
• Address and improve efficiency of timing, PnR, DRC and integration methodologies for DFx IPs.
• Develop new IPs and methodologies, including process characterization IP for test-vehicles.
• Define DFx Architecture for AMD’s next generation monolithic and stacked SoC product families, including testability, debug, characterization, repair and yield.
• Work with functional IP teams on integration, analysis and qualification methodologies for a growing number of DFx IPs, tools and flows.

Skills

RTL design

Timing constraints

Design methodologies

STA

RTL-DRC

CDC

RDC

Constraints checking

Perl

TCL

Python

Verilog simulation

Coverage analysis

Assertions

Scan design

ATPG

Memory BIST

Repair

Yield improvements

Education

Bachelors or Masters in Computer/Electrical Engineering

Job description

Advanced Micro Devices in California seeks a DFx engineer to define constraints for IPs, optimize timing, PnR and DFx methodologies across next‑gen monolithic and stacked SoCs. You will collaborate with IP teams to ensure testability, debug, characterization, repair and yield improvements.

The role requires strong analytical skills, RTL design/verification experience, and familiarity with DFx concepts. Hybrid work options near San Jose are available.