Senior DFT/DFX Lead for Neuromorphic SoC

Intel; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Health benefits

Retirement plan

Paid time off

Job summary

Intel is seeking a senior engineer to lead DFT/DFX for neuromorphic silicon. You will architect test strategies, drive fault coverage, and collaborate with circuit experts to enable high-volume manufacturing for Loihi family products.

Responsibilities include SoC-level scan, ATPG vector generation, and developing novel DFX methodologies for asynchronous circuits. This role supports a hybrid work model in the United States.

Qualifications

• Bachelor's degree in EE/CS or related field with 6+ years of DFT experience or Master's with 4+ years.
• 6+ years architecting the entire DFT stack including scan insertion, compression, and ATPG vector generation.
• 1 year debugging post-silicon and driving circuit changes for testability and reliability improvements.
• Experience with IP/SoC-level scan constructs (JTAG, TAP, BIST/MBIST).

Responsibilities

• Architect a complete DFT solution at the SoC level for synchronous and asynchronous designs.
• Lead flow-development for scan-insertion and compression at partition and SoC levels.
• Build a scalable framework spanning EDA tools, RTL and emulation models to generate and validate test vectors pre-silicon.
• Collaborate with designers to drive DFT/DFD/DFM features for manufacturing readiness to support high-volume manufacturing.
• Lead silicon power-on, enabling tester content, debugging failures and maintaining toolflows.

Skills

DFT/DFX

IP/SoC testability

System-Verilog / System-C / OOP

ATPG vector generation

JTAG / boundary scan

Debug post-silicon

AI tool flows

Asynchronous design techniques

Education

Bachelor's degree in Electrical Engineering or related

Master's degree (preferred)

Tools

EDA tools

RTL/Emulation models

Job description

Intel is seeking a senior engineer to lead DFT/DFX for neuromorphic silicon. You will architect test strategies, drive fault coverage, and collaborate with circuit experts to enable high-volume manufacturing for Loihi family products.

Responsibilities include SoC-level scan, ATPG vector generation, and developing novel DFX methodologies for asynchronous circuits. This role supports a hybrid work model in the United States.