DFT Program Lead - SoC Test & Yield

Broadcom, Inc.; Austin (TX); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grants

Competitive benefits package

Job summary

Broadcom's ASIC Product Division in Austin, Texas is seeking a DFT manager to lead the local DFT team from specification through to implementation and verification culminating in the production release. The role emphasizes DFT architecture, test insertion and verification, pattern generation, coverage improvement, post‑silicon debug, and yield enhancement in collaboration with the STA/DI teams.

Some hands‑on work will be required to support the DFT leads.

Qualifications

• Minimum 12+ years of relevant industry experience, with at least 3 years in management.
• Deep DFT experience across architecture, test insertion, verification, and yield improvement.
• Proficiency in Verilog and testbench simulation; strong debugging skills.
• Strong communication and cross‑functional leadership abilities.

Responsibilities

• Lead the local DFT team from spec through implementation and verification to production release.
• Define DFT specifications for ASICs and manage DFT feature sets (IO, Scan, MBIST, TAP, LBIST).
• Collaborate with STA/DI engineers for timing closure and with global teams for delivery.
• Provide hands‑on support and coaching to DFT leads; manage performance and career development.
• Drive silicon failure analysis, diagnostics, and yield improvement initiatives.
• Engage with customers and executive management as the primary DFT contact.

Skills

DFT basics

ATPG/Scan

Verilog

Debugging

Communication

Leadership

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Tessent SSN

TetraMax

Fastscan

TestKompress

Job description

Broadcom's ASIC Product Division in Austin, Texas is seeking a DFT manager to lead the local DFT team from specification through to implementation and verification culminating in the production release. The role emphasizes DFT architecture, test insertion and verification, pattern generation, coverage improvement, post‑silicon debug, and yield enhancement in collaboration with the STA/DI teams.

Some hands‑on work will be required to support the DFT leads.