Senior DFT Engineer - ASIC/SoC Test & Yield Excellence

The Consensus; San Jose (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Housing subsidy for office proximity

Relocation support for San Jose

Wellness benefits

Daily lunch + dinner in office

Unlimited compute budget

Job summary

Etched is seeking a highly skilled Design For Testability (DFT) Engineer to ensure robust testability of ICs from design to production. You will develop DFT architectures, integrate scan, boundary scan, BIST, MBIST, and work with design/verification teams to improve coverage and reliability.

The role spans post-silicon support and ATE program optimization. Expect extensive hands-on work with SystemVerilog, EDA tools, and scripting to drive testability across multiple product generations in a

Qualifications

• 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
• Deep understanding of digital design, verification methodologies, and DFT implementation practices.
• Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
• Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.
• Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
• Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues.
• Excellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment.
• A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).

Responsibilities

• Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs.
• Integrate DFT methodologies such as scan insertion, boundary scan, BIST, and MBIST.
• Collaborate with design and verification teams to address DFT requirements early in the design cycle.
• Analyze test results and silicon debug data to improve coverage, yield, and reliability.
• Create and execute DFT verification plans to validate implementation and functionality.
• Apply simulation-based and formal verification techniques to ensure DFT logic correctness.
• Conduct internal DFT audits and design reviews to identify gaps in testability or coverage.
• Support silicon bring-up, debug, and failure analysis during post-silicon validation.
• Partner with test engineering teams to develop and optimize ATE programs for volume production.
• Generate production-quality test patterns and enable robust failure analysis in high-volume environments.
• Collaborate with manufacturing and quality teams to implement data-driven test process improvements.
• Ensure test strategies align with product milestones, manufacturing timelines, and quality targets.
• Author and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides.
• Share best practices through training sessions, onboarding, and mentorship to enhance DFT awareness.
• Stay current with emerging DFT technologies and industry trends to improve methodologies.

Skills

SystemVerilog

DFT

EDA Tools

Python Scripting

Debugging

Cross-functional collaboration

Education

Bachelor's in Electrical Engineering

Master’s preferred

Tools

Synopsys DFT Compiler

Cadence Encounter Test

Mentor Tessent

Job description

Etched is seeking a highly skilled Design For Testability (DFT) Engineer to ensure robust testability of ICs from design to production. You will develop DFT architectures, integrate scan, boundary scan, BIST, MBIST, and work with design/verification teams to improve coverage and reliability.

The role spans post-silicon support and ATE program optimization. Expect extensive hands-on work with SystemVerilog, EDA tools, and scripting to drive testability across multiple product generations in a