Senior ASIC DFT Engineer - SoC Test & Silicon Debug

Google; United States; On-site; USD 163,000 - 237,000; Full time

Job summary

Google in Mountain View, CA seeks a Senior ASIC DFT Engineer with mid-level experience to lead DFT architecture and implementation across SOCs. You will work with RTL, DSP, and physical teams to push testability across all design stages and ensure robust silicon bring-up.

Responsibilities cover DFT architecture, SCAN/MBIST, and integration of DFT flows from design to post-silicon debugging. Strong scripting skills (Python/Perl) are valued.

Qualifications

• Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
• 8 years of experience with Design for Test (DFT).
• Experience with DFT EDA Tools (e.g., Tessent, Genus, Fusion Compiler (FC), Simvision).
• Experience with Scan insertion, ATPG, Gate Level Simulations and silicon debug.
• Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), IJTAG tools and flow.

Responsibilities

• Collaborate with multi-disciplined and multi-site teams of DFT engineers, RTL, Physical Designer Engineers, SOC DFT, and Product Engineering.
• Develop MBIST architecture and subsystem DFT with multiple voltage and power domains.
• Create tests for Production in the ATE flow and automate the DFT flow with scripts.
• Drive scan implementation and verification ensuring coverage across all fault models.
• Manage Gate-Level Simulation (GLS) verification, tape-out signoff, pattern delivery, and post-silicon bring-up and debug.

Skills

DFT

DFT EDA Tools

Scan insertion

ATPG

IJTAG

JTAG

BIST

Education

Bachelor's degree

Tools

Tessent

Genus

Fusion Compiler

Simvision

Job description

Google in Mountain View, CA seeks a Senior ASIC DFT Engineer with mid-level experience to lead DFT architecture and implementation across SOCs. You will work with RTL, DSP, and physical teams to push testability across all design stages and ensure robust silicon bring-up.

Responsibilities cover DFT architecture, SCAN/MBIST, and integration of DFT flows from design to post-silicon debugging. Strong scripting skills (Python/Perl) are valued.