DFT Tech Lead

Retym, Inc; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

Retym, Inc, based in Austin, Texas, is seeking a talented DFT Tech Lead to join their team. In this role, you will collaborate with various design teams and be responsible for defining and implementing advanced design-for-test methodologies for complex digital and mixed-signal chips.

The ideal candidate will have over 8 years of experience in DFT, silicon bring-up, and fault modeling, along with a Master’s degree in Electrical Engineering. Strong communication skills and attention to detail are essential.

Qualifications

• 8+ years of experience in DFT specification definition and architecture.
• Experience with silicon bring-up, debug, and validation of DFT features.
• Experience in fault modeling.

Responsibilities

• Create SoC DFT strategy and architecture.
• Work on hierarchical design.
• Debug all Design Rule checks.
• Insert DFT logic like boundary scan and scan chains.
• Define test plan for special analog IPs.

Skills

DFT specification definition

Silicon bring-up and debug

Fault modeling

Design/Fusion Compiler

DFT Max

SpyGlass

Modus

Tessent

TestKompress

ASIC DFT knowledge

Education

Master’s degree in Electrical Engineering

Job description

We are looking for a talented and experienced DFT Tech Lead.

As a DFT Tech Lead you will work closely with all other design teams – backend, VLSI, verification and analog, fully responsible for defining, implementing, and deploying advanced design-for-test (DFT) methodologies for highly complex digital and mixed-signal chips. You will define silicon test strategies, DFT/DFD architecture, and create DFT and Debug specifications for complex next generation SoCs.

Minimum qualifications

• 8+ years of experience in DFT specification definition, architecture, insertion, and analysis in designs
• Experience in silicon bring‑up, debug, and validation of DFT features on ATE, debugging ATPG patterns, compressed ATPG patterns, MBIST, and JTAG‑related issues
• Experience in fault modeling

Preferred qualifications

• Master’s degree in Electrical Engineering.
• Experience in IP integration (memories, Test controllers, TAP, MBIST).
• Experience using EDA Test tools like Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, and TestKompress.
• Experience and understanding of ASIC DFT, synthesis, simulation and verification flow.
• Excellent attention to detail, organizational, problem‑solving, and communication skills.

Responsibilities

• Create SoC DFT strategy and architecture (ATPG/DFT/MBIST)
• Work on hierarchical design
• Debug all Design Rule checks, apply design fixes to achieve high test quality
• Insert all DFT logic – boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
• Insert and hook up MBIST logic.
• Define test plan for special analog IPs and implement.
• Document DFT architecture and test sequences, including boot‑up sequence associated with test pins.