Senior DFT Engineer — ASIC/SoC Test & Debug Lead

Etched.ai, Inc.; San Jose (CA); On-site; USD 120,000 - 160,000; Full time

Benefits offered by this job

Medical, dental, and vision benefits

Housing subsidy of $2,000 per month

Relocation support

Daily lunch and dinner provided

Various wellness benefits

Job summary

Etched.ai, Inc. is seeking a Design For Testability (DFT) Engineer to enhance the testability of integrated circuits. The ideal candidate will develop DFT architectures, collaborate on design requirements, and ensure robust test strategies during production.

This position requires 10+ years of DFT experience in ASIC or SoC environments and offers comprehensive benefits including housing subsidies, wellness programs, and relocation support.

Qualifications

• 10+ years of experience in DFT engineering.
• Deep understanding of digital design and DFT practices.
• Ability to lead DFT initiatives in high-performance environments.

Responsibilities

• Develop DFT architectures for ASIC/SoC designs.
• Collaborate with teams to ensure DFT requirements are met.
• Conduct DFT audits and design reviews.

Skills

Design for Test (DFT)

Digital design

Verification methodologies

System Verilog

Python scripting

Debugging skills

Communication

Collaboration

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Synopsys DFT Compiler

Cadence Encounter Test

Mentor Tessent

Job description

Etched.ai, Inc. is seeking a Design For Testability (DFT) Engineer to enhance the testability of integrated circuits. The ideal candidate will develop DFT architectures, collaborate on design requirements, and ensure robust test strategies during production.

This position requires 10+ years of DFT experience in ASIC or SoC environments and offers comprehensive benefits including housing subsidies, wellness programs, and relocation support.