DFT Engineer

QFocus Technologies; Sunnyvale (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

QFocus Technologies in Sunnyvale, CA, is seeking a Senior DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs, collaborating with front-end, physical design, verification and product teams.

You will lead pre-silicon activities, implement DFT architectures (Scan, ATPG, MBIST, JTAG), and drive post-silicon bring-up and yield improvements in a fast-paced environment.

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development.

Responsibilities

• Pre-Silicon Execution: Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG.
• Pre-Silicon Execution: Perform Scan Chain Insertion, stitching, and optimization for timing closure and power grid compatibility.
• Pre-Silicon Execution: Integrate MBIST controllers, repair mechanisms, and memory test routines.
• Pre-Silicon Execution: Generate high-coverage ATPG patterns (Stuck-at, At-Speed, Cell-Aware).
• Pre-Silicon Execution: Execute Verilog/SystemVerilog simulations for gate-level DFT validation with SDF.
• Pre-Silicon Execution: Run DFT linting with SpyGlass DFT, Tessent, Modus, or TetraMAX.
• Post-Silicon Production & Bring-up: Translate ATPG/MBIST patterns into tester formats (WGL, STIL) for ATE deployment.
• Post-Silicon Production & Bring-up: Support post-silicon bring-up, debugging first-silicon DFT features, and pattern conversion.
• Collaborate with Product and Test Engineering teams to optimize test time and boost manufacturing yield.

Skills

Verilog / SystemVerilog

Scan Insertion

ATPG

MBIST

JTAG

Post-Silicon Support

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Position Overview

As a Senior DFT Engineer at QFocus Technologies, you will be responsible for defining, architecting, and executing robust Design-for-Test strategies for high-performance SoCs/ASICs. You will work closely with front-end design, physical design, verification, and product engineering teams to ensure high test coverage, optimal silicon quality, and streamlined post-silicon manufacturing test enablement.

Key Responsibilities

• Pre-Silicon Execution:
• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST, and JTAG / IEEE standards (1149.1, 1500, 1687 IJTAG).
• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure and power grid compatibility.
• Integrate Memory BIST (MBIST) controllers, repair mechanisms, and custom memory test routines.
• Generate high-coverage Automatic Test Pattern Generation (ATPG) patterns, including Stuck-at, At-Speed (Transition/Path Delay), and Cell-Aware testing.
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation, ensuring timing and vector cleanliness (SDF simulation).
• Run DFT linting and rule checking using industry-standard tools (e.g., SpyGlass DFT, Tessent, Modus, or TetraMAX)

• Post-Silicon Production & Bring-up:
• Translate pre-silicon ATPG and MBIST patterns into tester formats (e.g., WGL, STIL) for ATE (Automatic Test Equipment) deployment.
• Support post-silicon bring-up in the lab, debugging first-silicon DFT features, pattern conversion, and silicon failures.
• Collaborate with Product and Test Engineering (PTE) teams to optimize test time, diagnose failure modes, and boost manufacturing yield.

Required Qualifications

• Experience: 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
• Core Skills & Technical Expertise:
• Verilog / SystemVerilog: Strong proficiency in Hardware Description Languages for DFT integration, wrapper creation, and simulation debugging.
• Scan Insertion: Hands-on experience with scan synthesis, compressed scan architectures (EDT/SmartTest), and boundary scan integration.
• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.
• ATPG: Deep experience generating, debugging, and fault-grading Stuck-at, At-speed, and fault-model test patterns.
• MBIST: Proven experience with memory BIST insertion, MBIST architecture, and memory repair schemes.
• JTAG: Solid understanding of IEEE 1149.1 standards, TAP controllers, and board/chip-level test logic integration.
• Post-Silicon Support: Direct experience bringing up patterns on target silicon and supporting production yield ramp.

Preferred Skills

• Familiarity with scripting languages (Tcl, Python, or Perl) for automation of DFT flows.
• Knowledge of advanced DFT concepts like High-Speed IO testing, SerDes loopback, or Analog DFT.
• Understanding of synthesis tools (Synopsys Design Compiler, Cadence Genus) and static timing analysis (STA) constraint creation for DFT modes.