Senior DFT Engineer - Remote (ASIC/SoC)

Encore Semi Llc; Dallas (TX); Remote; USD 135,000 - 150,000; Full time

Benefits offered by this job

PTO 15 days per year

10 holidays per year

Medical benefits 80% premiums

Dental & Vision 50%

Life Insurance

401k Traditional & Roth

EAP

Tuition reimbursement

Long-Term Disability

Job summary

Encore Semi, Inc. seeks a Senior DFT Engineer to lead test architecture for complex SoCs.

This 100% remote role supports teams across the US and requires 8+ years in ASIC DFT, with strong IJTAG expertise and experience delivering RTL-to-silicon test flows. The position emphasizes DFT structure design (Scan, MBIST, Boundary Scan), IJTAG networks, and rigorous fault coverage, with base salary target between $135,000 and $150,000 plus a comprehensive benefits package.

Qualifications

• 8+ years of proven industry experience in ASIC DFT engineering.
• IEEE 1687 (IJTAG) architecture expertise, including ICL and PDL formats.
• Deep proficiency with Mentor Graphics Tessent tool suite.
• Solid simulation/verification and debug using Xcelium, VCS, or QuestaSim.
• Fluency in Verilog/SystemVerilog and strong scripting (Tcl, Python, Perl).

Responsibilities

• Architect, implement, and verify DFT structures (Scan, MBIST, Boundary Scan) for next-gen ASIC/SoC designs.
• Develop and integrate IJTAG networks across IP and SoC levels.
• Perform test insertion, ATPG generation, and rigorous fault coverage analysis.
• Run and debug zero-delay and timing-annotated gate-level simulations.

Skills

ASIC DFT

IJTAG (IEEE 1687)

Verilog/SystemVerilog

Scripting (Tcl/Python/Perl)

ATPG/DFT

Education

BS or MS in Electrical Engineering, Computer Engineering, or related field

Tools

Tessent

Xcelium

VCS

QuestaSim

Job description

Encore Semi, Inc. seeks a Senior DFT Engineer to lead test architecture for complex SoCs.

This 100% remote role supports teams across the US and requires 8+ years in ASIC DFT, with strong IJTAG expertise and experience delivering RTL-to-silicon test flows. The position emphasizes DFT structure design (Scan, MBIST, Boundary Scan), IJTAG networks, and rigorous fault coverage, with base salary target between $135,000 and $150,000 plus a comprehensive benefits package.