Senior DFT Engineer for SoC Test & Validation

Rivian Automotive; Palo Alto (CA); On-site; USD 186,000 - 232,000; Full time

Benefits offered by this job

401(k) Plan

Employee Stock Purchase Program

Comprehensive benefits package

Job summary

Rivian Automotive is seeking a DFT Engineer in the San Francisco Bay Area to define, implement, and deploy advanced DFT methodologies across RTL to post-silicon. You will own DFT insertion, verification, DRC checks, and test-coverage closure while collaborating with RTL, physical design, and productization teams.

The role requires experience with scan, MBIST, JTAG/iJTAG, mixed-signal tests, UPF, and formal verification, plus strong scripting for automation.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 5+ years of DFT architecture, implementation, and verification for SoCs.
• Experience with DFT tools and IP integration.
• Proficient Verilog design experience.
• Familiarity with SDC and STA/Debug.

Responsibilities

• Lead implementation of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, logic BIST, Functional Safety(FuSa) and Analog IP Tests.
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
• Integration and verification of DFT fabrics and IP within Subsystems
• Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell- aware, path delay fault models, diagnosis, and hierarchical test flows.
• Run and debug non-timing and SDF annotated gate level simulations
• Analyze test results and drive test coverage improvement and closure
• Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization
• Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing
• Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies.

Skills

DFT Architecture

ATPG basics

Verilog

Scripting (Python, Tcl, Perl)

Gate-level timing analysis

Education

Bachelor's degree in Electrical Engineering or equivalent

Tools

Synopsys Fusion Compiler

TestMax

Siemens Tessent

Tessent TestKompress

Scripting languages (Python, Tcl, Perl)

Job description

Rivian Automotive is seeking a DFT Engineer in the San Francisco Bay Area to define, implement, and deploy advanced DFT methodologies across RTL to post-silicon. You will own DFT insertion, verification, DRC checks, and test-coverage closure while collaborating with RTL, physical design, and productization teams.

The role requires experience with scan, MBIST, JTAG/iJTAG, mixed-signal tests, UPF, and formal verification, plus strong scripting for automation.