DFT Engineer - SoC/ASIC Test & Validation

MatchPoint; San Francisco (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

MatchPoint in San Francisco is seeking a DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs. You will collaborate with front-end design, verification, and product engineering to ensure high test coverage and streamlined manufacturing test enablement.

The role covers pre-silicon execution, memory test, and post-silicon bring-up, with hands-on work in scan insertion, MBIST, JTAG, and ATPG, and interactions with PTE teams to optimize test time and

Qualifications

• 3+ years of hands-on DFT experience in advanced SoC/ASIC development nodes.
• Verilog/SystemVerilog: strong proficiency for DFT integration, wrapper creation and simulation debugging.
• Scan Insertion: hands-on with scan synthesis, boundary scan integration.
• ATPG: deep experience generating, debugging, and fault-grading Stuck-at, At-speed.
• MBIST: experience with memory BIST insertion and memory repair schemes.
• JTAG: solid understanding of IEEE 1149.1 and TAP controllers.
• Post-Silicon Support: direct experience bringing up patterns on target silicon and production yield ramp.

Responsibilities

• Define and implement comprehensive DFT architectures including Scan, ATPG, MBIST and JTAG/IEEE standards.
• Perform Scan Chain Insertion, stitching, and optimization to ensure timing closure.
• Integrate MBIST controllers, repair mechanisms, and custom memory test routines.
• Handle Stuck-at, At-Speed and Cell-Aware testing.
• Execute Verilog/SystemVerilog simulations for gate-level DFT validation with timing and vector cleanliness.
• Run DFT linting and rule checks using SpyGlass DFT, Tessent, Modus or TetraMAX.
• Translate pre-silicon ATPG/MBIST patterns into tester formats (WGL, STIL) for ATE deployment.
• Support post-silicon bring-up in the lab and collaborate with PTE teams to optimize test time and yield.

Skills

Verilog

SystemVerilog

Scan Insertion

ATPG

MBIST

JTAG

IEEE 1149.1

Tools

SpyGlass DFT

Tessent

Modus

TetraMAX

Job description

MatchPoint in San Francisco is seeking a DFT Engineer to define and execute robust Design-for-Test strategies for high-performance SoCs/ASICs. You will collaborate with front-end design, verification, and product engineering to ensure high test coverage and streamlined manufacturing test enablement.

The role covers pre-silicon execution, memory test, and post-silicon bring-up, with hands-on work in scan insertion, MBIST, JTAG, and ATPG, and interactions with PTE teams to optimize test time and