Senior ASIC DFT Engineer for SoC Test

Watershed; Palo Alto (CA); On-site; USD 186,000 - 232,000; Full time

Benefits offered by this job

401(k) Plan

Employee Stock Purchase Program

Job summary

Rivian is seeking an experienced DFT Engineer in the San Francisco Bay Area to design, implement, and verify advanced DFT solutions for complex SoCs. You will own DFT insertion, verification, timing constraints, and post-silicon support, collaborating with RTL, physical design, and productization teams.

You will work with Scantors, MBIST/IP tests, ATPG, UPF, and mixed-signal DFT topics while using Perl/Python/Tcl to automate tests and data analysis.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience.
• 5+ years of experience in DFT architecture, implementation, and verification for SoCs.
• Experience in DFT flow, including architecture, IP integration (e.g., Scan controllers, TAP, MBIST), and interaction with synthesis and verification flows.
• Verilog design experience and familiarity with functional verification
• DFT SDC Creations and Test mode Static Timing Analysis & Debug
• Gate level simulation with timing & no-timing, debugging.
• Experience in ATE debug, or validation of DFT features.

Responsibilities

• Lead implementation of DFT architectures, including scan, compression/decompression logic, memory BIST, logic BIST, Functional Safety and Analog IP Tests.
• Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan DRC tools.
• Integration and verification of DFT fabrics and IP within Subsystems.
• Develop test scripts, automate processes, and analyze data using Perl, Python, Tcl.
• Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, Cell-aware, path delay fault models, diagnosis, and hierarchical test flows.
• Run and debug non-timing and SDF annotated gate level simulations.
• Analyze test results and drive test coverage improvement and closure.
• Develop ,validate and timing closure of DFT timing constraints for scan, BIST, and test modes.
• Experience with UPF (Unified Power Format), formal verification, and DRC rule checking experience.
• Support pre-silicon DFT signoff and assist with post-silicon pattern bring-up, debug and Silicon characterization.
• Exposure to mixed-signal or SERDES DFT, such as IOBIST or loopback testing.
• Exposure to Chiplet-based architectures, including Die-to-Die (D2D) test methodologies (e.g., UCIe interfaces) and Known Good Die (KGD) strategies.

Skills

DFT architecture

Verilog design

ATPG

Synthesis & verification flows

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent experience

Tools

Fusion Compiler

TestMax

Tessent

TestKompress

Job description

Rivian is seeking an experienced DFT Engineer in the San Francisco Bay Area to design, implement, and verify advanced DFT solutions for complex SoCs. You will own DFT insertion, verification, timing constraints, and post-silicon support, collaborating with RTL, physical design, and productization teams.

You will work with Scantors, MBIST/IP tests, ATPG, UPF, and mixed-signal DFT topics while using Perl/Python/Tcl to automate tests and data analysis.